SAM9G25 Atmel Corporation, SAM9G25 Datasheet - Page 20

• Manufacturer Part Number: SAM9G25
• Manufacturer: Atmel Corporation

Specifications of SAM9G25

• Flash (kbytes): 0 Kbytes
• Pin Count: 247
• Max. Operating Frequency: 400 MHz
• Cpu: ARM926
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 105
• Ext Interrupts: 105
• Usb Transceiver: 3
• Usb Speed: Hi-Speed
• Usb Interface: Host, Device
• Spi: 2
• Twi (i2c): 3
• Uart: 7
• Lin: 4
• Ssc: 1
• Ethernet: 1
• Sd / Emmc: 2
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: Yes
• Adc Channels: 12
• Adc Resolution (bits): 10
• Adc Speed (ksps): 440
• Resistive Touch Screen: No
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 32
• Self Program Memory: NO
• External Bus Interface: 1
• Dram Memory: DDR2/LPDDR, SDRAM/LPSDR
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8/3.3
• Operating Voltage (vcc): 0.9 to 1.1
• Fpu: No
• Mpu / Mmu: No/Yes
• Timers: 6
• Output Compare Channels: 6
• Input Capture Channels: 6
• Pwm Channels: 4
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: No

Table 4-4.
20
W18
Ball
M14
N14
P18
R10
P10
U13
U12
V15
D17
M10
P13
P17
U11
U14
G15
K10
M11
R11
U18
V19
V18
E15
C16
D15
F17
L10
L11
F14
M9
N8
E8
F7
E7
F6
E6
H8
K9
C6
J5
J9
L8
VDDUTMIC
Power Rail
VDDCORE
VDDCORE
VDDCORE
VDDCORE
VDDCORE
VDDCORE
VDDCORE
VDDCORE
VDDCORE
VDDCORE
GNDCORE
GNDCORE
GNDCORE
GNDCORE
GNDCORE
GNDCORE
GNDCORE
GNDCORE
GNDCORE
VDDUTMII
VDDPLLA
GNDUTMI
VDDIOP0
VDDIOP0
VDDIOP1
GNDOSC
VDDANA
GNDANA
VDDOSC
GNDIOM
GNDIOM
GNDIOM
GNDIOP
GNDIOP
GNDIOP
VDDIOM
VDDIOM
VDDIOM
VDDIOM
GNDBU
VDDBU
SAM9G25
Pin Description BGA247 (Continued)
I/O Type
POWER
POWER
POWER
POWER
POWER
POWER
POWER
POWER
POWER
POWER
POWER
POWER
POWER
POWER
POWER
POWER
POWER
POWER
POWER
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
EBI
EBI
EBI
EBI
VDDUTMIC
GNDCORE
GNDCORE
GNDCORE
GNDCORE
GNDCORE
GNDCORE
GNDCORE
GNDCORE
GNDCORE
VDDCORE
VDDCORE
VDDCORE
VDDCORE
VDDCORE
VDDCORE
VDDCORE
VDDCORE
VDDCORE
VDDUTMII
GNDUTMI
VDDIOP0
VDDIOP0
VDDIOP1
GNDANA
VDDOSC
GNDOSC
GNDIOM
GNDIOM
GNDIOM
VDDANA
GNDIOP
GNDIOP
GNDIOP
VDDPLL
VDDBU
GNDBU
Signal
PD1
D0
D1
D2
D3
Primary
Dir
I/O
I/O
I/O
I/O
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
Signal
Alternate
Dir
PIO Peripheral A
Signal
Dir
PIO Peripheral B
Signal
Dir
PIO Peripheral C
Signal
11032A–ATARM–27-Jul-11
Dir
Signal, Dir, PU,
Reset State
PD, ST
O, PD
O, PD
O, PD
O, PD
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I