SAM9G25 Atmel Corporation, SAM9G25 Datasheet - Page 22

• Manufacturer Part Number: SAM9G25
• Manufacturer: Atmel Corporation

Specifications of SAM9G25

• Flash (kbytes): 0 Kbytes
• Pin Count: 247
• Max. Operating Frequency: 400 MHz
• Cpu: ARM926
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 105
• Ext Interrupts: 105
• Usb Transceiver: 3
• Usb Speed: Hi-Speed
• Usb Interface: Host, Device
• Spi: 2
• Twi (i2c): 3
• Uart: 7
• Lin: 4
• Ssc: 1
• Ethernet: 1
• Sd / Emmc: 2
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: Yes
• Adc Channels: 12
• Adc Resolution (bits): 10
• Adc Speed (ksps): 440
• Resistive Touch Screen: No
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 32
• Self Program Memory: NO
• External Bus Interface: 1
• Dram Memory: DDR2/LPDDR, SDRAM/LPSDR
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8/3.3
• Operating Voltage (vcc): 0.9 to 1.1
• Fpu: No
• Mpu / Mmu: No/Yes
• Timers: 6
• Output Compare Channels: 6
• Input Capture Channels: 6
• Pwm Channels: 4
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: No

Table 4-4.
22
W19
Ball
G10
C11
H10
B11
E10
B10
U16
U17
V16
V17
R17
R18
M18
N18
V10
V11
U10
V13
V12
V14
J10
T17
T18
G9
B6
E9
F9
R9
F8
C8
V9
V8
R8
P8
U9
P9
C7
B7
B8
Not Connected
Not Connected
VDDUTMIC
Power Rail
VDDUTMII
VDDUTMII
VDDUTMII
VDDUTMII
VDDUTMII
VDDUTMII
VDDUTMII
VDDUTMII
VDDUTMII
VDDUTMII
VDDIOP0
VDDIOP0
VDDIOP0
VDDIOP0
VDDIOP0
VDDIOP0
VDDIOP0
VDDIOP0
VDDIOP0
VDDIOP0
VDDANA
VDDOSC
VDDOSC
VDDIOM
VDDIOM
VDDIOM
VDDIOM
VDDIOM
VDDIOM
VDDIOM
VDDIOM
VDDBU
VDDBU
VDDBU
VDDBU
VDDBU
VDDBU
SAM9G25
Pin Description BGA247 (Continued)
RSTJTAG
RSTJTAG
RSTJTAG
RSTJTAG
RSTJTAG
RSTJTAG
RSTJTAG
RSTJTAG
I/O Type
POWER
USBFS
USBFS
USBHS
USBHS
USBFS
USBFS
USBHS
USBHS
USBFS
USBFS
CLOCK
CLOCK
CLOCK
CLOCK
EBI_O
EBI_O
EBI_O
EBI_O
EBI_O
EBI_O
SYSC
SYSC
SYSC
SYSC
VBG
DIB
DIB
EBI
EBI
HHSDMA
HHSDMB
HFSDMC
JTAGSEL
HFSDMA
HHSDPA
HFSDPB
HFSDMB
HHSDPB
HFSDPC
ADVREF
HFSDPA
XOUT32
NTRST
SDA10
Signal
SDWE
DQM0
DQM1
WKUP
SHDN
DQS0
DQS1
RTCK
NRST
XIN32
XOUT
DIBN
DIBP
RAS
CAS
VBG
BMS
TCK
TDO
TMS
TST
TDI
XIN
Primary
Dir
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
O
O
O
O
O
O
O
O
O
O
O
I
I
I
I
I
I
I
I
I
I
I
I
DHSDM
DFSDM
DHSDP
DFSDP
Signal
Alternate
Dir
I/O
I/O
I/O
I/O
PIO Peripheral A
Signal
Dir
PIO Peripheral B
Signal
Dir
PIO Peripheral C
Signal
11032A–ATARM–27-Jul-11
Dir
Signal, Dir, PU,
Reset State
I, PD, ST
I, PD, ST
I, PU, ST
I, PU, ST
PD, ST
O, PU
O, PU
O, PU
O, PU
O, PU
O, PU
O, PD
O, PD
O, PD
O, PD
O, PD
O, PD
O, PD
O, PD
O, PD
O, PD
O, PD
O, PD
O, PU
O, PU
O, PU
I, ST
I, PD
I, ST
I, ST
I, ST
O
O
O
O
I
I
I
I