SAM9G25 Atmel Corporation, SAM9G25 Datasheet - Page 302

• Manufacturer Part Number: SAM9G25
• Manufacturer: Atmel Corporation

Specifications of SAM9G25

• Flash (kbytes): 0 Kbytes
• Pin Count: 247
• Max. Operating Frequency: 400 MHz
• Cpu: ARM926
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 105
• Ext Interrupts: 105
• Usb Transceiver: 3
• Usb Speed: Hi-Speed
• Usb Interface: Host, Device
• Spi: 2
• Twi (i2c): 3
• Uart: 7
• Lin: 4
• Ssc: 1
• Ethernet: 1
• Sd / Emmc: 2
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: Yes
• Adc Channels: 12
• Adc Resolution (bits): 10
• Adc Speed (ksps): 440
• Resistive Touch Screen: No
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 32
• Self Program Memory: NO
• External Bus Interface: 1
• Dram Memory: DDR2/LPDDR, SDRAM/LPSDR
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8/3.3
• Operating Voltage (vcc): 0.9 to 1.1
• Fpu: No
• Mpu / Mmu: No/Yes
• Timers: 6
• Output Compare Channels: 6
• Input Capture Channels: 6
• Pwm Channels: 4
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: No

25.2.1
25.2.2
302
SAM9G25
Matrix Masters
Matrix Slaves
The Bus Matrix manages 12 masters, which means that each master can perform an access
concurrently with others, depending on whether the slave it accesses is available.
Each master has its own decoder, which can be defined specifically for each master. In order to
simplify the addressing, all the masters have the same decodings.
Table 25-1.
The Bus Matrix manages 9 slaves. Each slave has its own arbiter, thus allowing a different arbi-
tration per slave to be programmed.
Table 25-2.
Master 0
Master 1
Master 2&3
Master 4&5
Master 6
Master 7
Master 8
Master 9
Master 10
Slave 0
Slave 1
Slave 2
Slave 3
Slave 4
Slave 5
Slave 6
Slave 7
Slave 8
Slave 9
List of Bus Matrix Masters
List of Bus Matrix Slaves
Internal SRAM
Internal ROM
Soft Modem (SMD)
USB Device High Speed Dual Port RAM (DPR)
USB Host EHCI registers
USB Host OHCI registers
External Bus Interface
DDR2 port 1
DDR2 port 2
DDR2 port 3
Peripheral Bridge 0
Peripheral Bridge 1
ARM926 Instruction
ARM926 Data
DMA Controller 0
DMA Controller 1
UDP HS DMA
UHP EHCI DMA
UHP OHCI DMA
ISI DMA
EMAC DMA
11032A–ATARM–27-Jul-11