SAM9G25 Atmel Corporation, SAM9G25 Datasheet - Page 462

• Manufacturer Part Number: SAM9G25
• Manufacturer: Atmel Corporation

Specifications of SAM9G25

• Flash (kbytes): 0 Kbytes
• Pin Count: 247
• Max. Operating Frequency: 400 MHz
• Cpu: ARM926
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 105
• Ext Interrupts: 105
• Usb Transceiver: 3
• Usb Speed: Hi-Speed
• Usb Interface: Host, Device
• Spi: 2
• Twi (i2c): 3
• Uart: 7
• Lin: 4
• Ssc: 1
• Ethernet: 1
• Sd / Emmc: 2
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: Yes
• Adc Channels: 12
• Adc Resolution (bits): 10
• Adc Speed (ksps): 440
• Resistive Touch Screen: No
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 32
• Self Program Memory: NO
• External Bus Interface: 1
• Dram Memory: DDR2/LPDDR, SDRAM/LPSDR
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8/3.3
• Operating Voltage (vcc): 0.9 to 1.1
• Fpu: No
• Mpu / Mmu: No/Yes
• Timers: 6
• Output Compare Channels: 6
• Input Capture Channels: 6
• Pwm Channels: 4
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: No

30.7.1
Name:
Address:
Access:
Reset:
This register can only be written if the bit WPEN is cleared in
• MODE: DDRSDRC Command Mode
This field defines the command issued by the DDRSDRC when the SDRAM device is accessed. This register is used to ini-
tialize the SDRAM device and to activate deep power-down mode.
462
462
MODE
000
001
010
011
100
101
110
111
31
23
15
–
–
–
7
–
SAM9G25
SAM9G25
DDRSDRC Mode Register
Description
Normal Mode. Any access to the DDRSDRC will be decoded normally. To activate this mode, command must be followed
by a write to the SDRAM.
The DDRSDRC issues a NOP command when the SDRAM device is accessed regardless of the cycle. To activate this
mode, command must be followed by a write to the SDRAM.
The DDRSDRC issues an “All Banks Precharge” command when the SDRAM device is accessed regardless of the cycle.
To activate this mode, command must be followed by a write to the SDRAM.
The DDRSDRC issues a “Load Mode Register” command when the SDRAM device is accessed regardless of the cycle.
To activate this mode, command must be followed by a write to the SDRAM.
The DDRSDRC issues an “Auto-Refresh” Command when the SDRAM device is accessed regardless of the cycle.
Previously, an “All Banks Precharge” command must be issued. To activate this mode, command must be followed by a
write to the SDRAM.
The DDRSDRC issues an “Extended Load Mode Register” command when the SDRAM device is accessed regardless of
the cycle. To activate this mode, the “Extended Load Mode Register” command must be followed by a write to the SDRAM.
The write in the SDRAM must be done in the appropriate bank.
Deep power mode: Access to deep power-down mode
Reserved
30
22
14
DDRSDRC_MR
0xFFFFE800
Read-write
See
–
–
–
6
–
Table 30-16
29
21
13
–
–
–
5
–
28
20
12
–
–
–
4
–
“DDRSDRC Write Protect Mode Register” on page
27
19
11
–
–
–
3
–
26
18
10
–
–
–
2
MODE
25
17
–
–
9
–
1
11032A–ATARM–27-Jul-11
11032A–ATARM–27-Jul-11
476.
24
16
–
–
8
–
0