SAM9G25 Atmel Corporation, SAM9G25 Datasheet - Page 456

• Manufacturer Part Number: SAM9G25
• Manufacturer: Atmel Corporation

Specifications of SAM9G25

• Flash (kbytes): 0 Kbytes
• Pin Count: 247
• Max. Operating Frequency: 400 MHz
• Cpu: ARM926
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 105
• Ext Interrupts: 105
• Usb Transceiver: 3
• Usb Speed: Hi-Speed
• Usb Interface: Host, Device
• Spi: 2
• Twi (i2c): 3
• Uart: 7
• Lin: 4
• Ssc: 1
• Ethernet: 1
• Sd / Emmc: 2
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: Yes
• Adc Channels: 12
• Adc Resolution (bits): 10
• Adc Speed (ksps): 440
• Resistive Touch Screen: No
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 32
• Self Program Memory: NO
• External Bus Interface: 1
• Dram Memory: DDR2/LPDDR, SDRAM/LPSDR
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8/3.3
• Operating Voltage (vcc): 0.9 to 1.1
• Fpu: No
• Mpu / Mmu: No/Yes
• Timers: 6
• Output Compare Channels: 6
• Input Capture Channels: 6
• Pwm Channels: 4
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: No

30.5.6
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SAM9G25
SAM9G25
Write Protected Registers
To prevent any single software error that may corrupt DDRSDRC behavior, the registers listed
below can be write-protected by setting the WPEN bit in the DDRSDRC Write Protect Mode
Register (DDRSDRC_WPMR).
If a write access in a write-protected register is detected, then the WPVS flag in the DDRSDRC
Write Protect Status Register (DDRSDRC_WPSR) is set and the field WPVSRC indicates in
which register the write access has been attempted.
The WPVS flag is automatically reset after reading the DDRSDRC Write Protect Status Register
(DDRSDRC_WPSR).
Following is a list of the write protected registers:
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“DDRSDRC Mode Register” on page 462
“DDRSDRC Refresh Timer Register” on page 463
“DDRSDRC Configuration Register” on page 464
“DDRSDRC Timing Parameter 0 Register” on page 467
“DDRSDRC Timing Parameter 1 Register” on page 469
“DDRSDRC Timing Parameter 2 Register” on page 470
“DDRSDRC Memory Device Register” on page 473
“DDRSDRC High Speed Register” on page 475
11032A–ATARM–27-Jul-11
11032A–ATARM–27-Jul-11