SAM9G25 Atmel Corporation, SAM9G25 Datasheet - Page 709

• Manufacturer Part Number: SAM9G25
• Manufacturer: Atmel Corporation

Specifications of SAM9G25

• Flash (kbytes): 0 Kbytes
• Pin Count: 247
• Max. Operating Frequency: 400 MHz
• Cpu: ARM926
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 105
• Ext Interrupts: 105
• Usb Transceiver: 3
• Usb Speed: Hi-Speed
• Usb Interface: Host, Device
• Spi: 2
• Twi (i2c): 3
• Uart: 7
• Lin: 4
• Ssc: 1
• Ethernet: 1
• Sd / Emmc: 2
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: Yes
• Adc Channels: 12
• Adc Resolution (bits): 10
• Adc Speed (ksps): 440
• Resistive Touch Screen: No
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 32
• Self Program Memory: NO
• External Bus Interface: 1
• Dram Memory: DDR2/LPDDR, SDRAM/LPSDR
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8/3.3
• Operating Voltage (vcc): 0.9 to 1.1
• Fpu: No
• Mpu / Mmu: No/Yes
• Timers: 6
• Output Compare Channels: 6
• Input Capture Channels: 6
• Pwm Channels: 4
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: No

36.6.4
11032A–ATARM–27-Jul-11
11032A–ATARM–27-Jul-11
Clock Control
Figure 36-3. Clock Selection
The clock of each counter can be controlled in two different ways: it can be enabled/disabled
and started/stopped. See
•
•
The clock can be enabled or disabled by the user with the CLKEN and the CLKDIS
commands in the Control Register. In Capture Mode it can be disabled by an RB load event
if LDBDIS is set to 1 in TC_CMR. In Waveform Mode, it can be disabled by an RC Compare
event if CPCDIS is set to 1 in TC_CMR. When disabled, the start or the stop actions have no
effect: only a CLKEN command in the Control Register can re-enable the clock. When the
clock is enabled, the CLKSTA bit is set in the Status Register.
The clock can also be started or stopped: a trigger (software, synchro, external or compare)
always starts the clock. The clock can be stopped by an RB load event in Capture Mode
(LDBSTOP = 1 in TC_CMR) or a RC compare event in Waveform Mode (CPCSTOP = 1 in
TC_CMR). The start and the stop commands have effect only if the clock is enabled.
TIMER_CLOCK1
TIMER_CLOCK2
TIMER_CLOCK3
TIMER_CLOCK4
TIMER_CLOCK5
XC0
XC1
XC2
Figure
1
TCCLKS
BURST
36-4.
Edge Detection
Synchronous
MCK
CLKI
Selected
Clock
SAM9G25
SAM9G25
709
709