SAM9G25 Atmel Corporation, SAM9G25 Datasheet - Page 919

• Manufacturer Part Number: SAM9G25
• Manufacturer: Atmel Corporation

Specifications of SAM9G25

• Flash (kbytes): 0 Kbytes
• Pin Count: 247
• Max. Operating Frequency: 400 MHz
• Cpu: ARM926
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 105
• Ext Interrupts: 105
• Usb Transceiver: 3
• Usb Speed: Hi-Speed
• Usb Interface: Host, Device
• Spi: 2
• Twi (i2c): 3
• Uart: 7
• Lin: 4
• Ssc: 1
• Ethernet: 1
• Sd / Emmc: 2
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: Yes
• Adc Channels: 12
• Adc Resolution (bits): 10
• Adc Speed (ksps): 440
• Resistive Touch Screen: No
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 32
• Self Program Memory: NO
• External Bus Interface: 1
• Dram Memory: DDR2/LPDDR, SDRAM/LPSDR
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8/3.3
• Operating Voltage (vcc): 0.9 to 1.1
• Fpu: No
• Mpu / Mmu: No/Yes
• Timers: 6
• Output Compare Channels: 6
• Input Capture Channels: 6
• Pwm Channels: 4
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: No

41. Analog-to-Digital Converter (ADC)
41.1
41.2
11032A–ATARM–27-Jul-11
11032A–ATARM–27-Jul-11
Description
Embedded Characteristics
The ADC is based on a 10-bit Analog-to-Digital Converter (ADC) managed by an ADC Control-
ler. Refer to the Block Diagram:
making possible the analog-to-digital conversions of 12 analog lines. The conversions extend
from 0V to ADVREF. The ADC supports an 8-bit or 10-bit resolution mode, and conversion
results are reported in a common register for all channels, as well as in a channel-dedicated reg-
ister. Software trigger, external trigger on rising edge of the ADTRG pin or internal triggers from
Timer Counter output(s) are configurable.
The comparison circuitry allows automatic detection of values below a threshold, higher than a
threshold, in a given range or outside the range, thresholds and ranges being fully configurable.
The ADC also integrates a Sleep Mode and a conversion sequencer and connects with a DMA
channel. These features reduce both power consumption and processor intervention.
age node that may be equal to the analog supply voltage. An external decoupling capacitance is
required for noise filtering.
Finally, the user can configure ADC timings, such as Startup Time and Tracking Time.
A whole set of reference voltages is generated internally from a single external reference volt-
• 10-bit Resolution
• TBD Hz Conversion Rate
• Wide Range Power Supply Operation
• Programmable Pen Detection sensitivity
• Integrated Multiplexer Offering Up to 12 Independent Analog Inputs
• Individual Enable and Disable of Each Channel
• Hardware or Software Trigger
• DMA Support
• Possibility of ADC Timings Configuration
• Two Sleep Modes and Conversion Sequencer
• Standby Mode for Fast Wakeup Time Response
• Automatic Window Comparison of Converted Values
• Write Protect Registers
– External Trigger Pin
– Internal Trigger Counter
– Automatic Wakeup on Trigger and Back to Sleep Mode after Conversions of all
– Possibility of Customized Channel Sequence
– Power Down Capability
Enabled Channels
Figure
41-1. It also integrates a 12-to-1 analog multiplexer,
SAM9G25
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