SAM9G25 Atmel Corporation, SAM9G25 Datasheet - Page 1106

• Manufacturer Part Number: SAM9G25
• Manufacturer: Atmel Corporation

Specifications of SAM9G25

• Flash (kbytes): 0 Kbytes
• Pin Count: 247
• Max. Operating Frequency: 400 MHz
• Cpu: ARM926
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 105
• Ext Interrupts: 105
• Usb Transceiver: 3
• Usb Speed: Hi-Speed
• Usb Interface: Host, Device
• Spi: 2
• Twi (i2c): 3
• Uart: 7
• Lin: 4
• Ssc: 1
• Ethernet: 1
• Sd / Emmc: 2
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: Yes
• Adc Channels: 12
• Adc Resolution (bits): 10
• Adc Speed (ksps): 440
• Resistive Touch Screen: No
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 32
• Self Program Memory: NO
• External Bus Interface: 1
• Dram Memory: DDR2/LPDDR, SDRAM/LPSDR
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8/3.3
• Operating Voltage (vcc): 0.9 to 1.1
• Fpu: No
• Mpu / Mmu: No/Yes
• Timers: 6
• Output Compare Channels: 6
• Input Capture Channels: 6
• Pwm Channels: 4
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: No

46.14.2.2
Table 46-28. SMC Read Signals - NRD Controlled (READ_MODE= 1)
Table 46-29. SMC Read Signals - NCS Controlled (READ_MODE= 0)
1106
1106
Symbol
SMC
SMC
SMC
SMC
SMC
SMC
SMC
Symbol
SMC
SMC
SMC
SMC
SMC
SMC
SMC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
SAM9G25
SAM9G25
Read Timings
Parameter
VDDIOM supply
Data Setup before NRD High
Data Hold after NRD High
Data Setup before NRD High
Data Hold after NRD High
A25 Valid before NRD High
NCS low before NRD High
NRD Pulse Width
Parameter
VDDIOM supply
Data Setup before NCS High
Data Hold after NCS High
Data Setup before NCS High
Data Hold after NCS High
NBS0/A0, NBS1, NBS2/A1, NBS3, A2 -
A25 valid before NCS High
NRD low before NCS High
NCS Pulse Width
NBS0/A0, NBS1, NBS2/A1, NBS3, A2 -
HOLD or NO HOLD SETTINGS (ncs rd hold
HOLD or NO HOLD SETTINGS (nrd hold
NO HOLD SETTINGS (ncs rd hold = 0)
NO HOLD SETTINGS (nrd hold = 0)
HOLD SETTINGS (ncs rd hold
HOLD SETTINGS (nrd hold
(ncs rd setup + ncs rd pulse - nrd
ncs rd pulse length * t
(nrd setup + nrd pulse)* t
(nrd setup + nrd pulse - ncs rd
(ncs rd setup + ncs rd pulse)*
nrd pulse * t
setup) * t
setup)* t
t
CPMCK
1.8V
1.8V
13.6
10.9
26.9
12.3
4.7
CPMCK
CPMCK
0
0
0
0
- 18.4
CPMCK
- 2.0
- 4.3
CPMCK
0)
- 3.2
0, ncs rd hold = 0)
0, nrd hold =0)
0)
CPMCK
- 4.0
Min
Min
-
ncs rd setup) * t
(ncs rd setup + ncs rd pulse
ncs rd pulse length * t
(nrd setup + nrd pulse)*
- nrd setup)* t
(nrd setup + nrd pulse -
nrd pulse * t
(ncs rd setup + ncs rd
pulse)* t
t
CPMCK
3.3V
11.7
3.3V
- 4.0
25.0
10.4
9.0
CPMCK
0
0
0
0
CPMCK
- 4.7
CPMCK
CPMCK
- 18.4
11032A–ATARM–27-Jul-11
11032A–ATARM–27-Jul-11
- 3.3
- 2.1
CPMCK
- 4.4
Units
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns