SAM9G25 Atmel Corporation, SAM9G25 Datasheet - Page 414

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SAM9G25

Manufacturer Part Number
SAM9G25
Description
Manufacturer
Atmel Corporation
Datasheets

Specifications of SAM9G25

Flash (kbytes)
0 Kbytes
Pin Count
247
Max. Operating Frequency
400 MHz
Cpu
ARM926
Hardware Qtouch Acquisition
No
Max I/o Pins
105
Ext Interrupts
105
Usb Transceiver
3
Usb Speed
Hi-Speed
Usb Interface
Host, Device
Spi
2
Twi (i2c)
3
Uart
7
Lin
4
Ssc
1
Ethernet
1
Sd / Emmc
2
Graphic Lcd
No
Video Decoder
No
Camera Interface
Yes
Adc Channels
12
Adc Resolution (bits)
10
Adc Speed (ksps)
440
Resistive Touch Screen
No
Temp. Sensor
No
Crypto Engine
No
Sram (kbytes)
32
Self Program Memory
NO
External Bus Interface
1
Dram Memory
DDR2/LPDDR, SDRAM/LPSDR
Nand Interface
Yes
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.8/3.3
Operating Voltage (vcc)
0.9 to 1.1
Fpu
No
Mpu / Mmu
No/Yes
Timers
6
Output Compare Channels
6
Input Capture Channels
6
Pwm Channels
4
32khz Rtc
Yes
Calibrated Rc Oscillator
No
29.12.4
Figure 29-30. NWAIT Latency
11032A–ATARM–27-Jul-11
11032A–ATARM–27-Jul-11
intenally synchronized
NWAIT signal
NBS0, NBS1,
NBS2, NBS3,
A0,A1
NWAIT Latency and Read/Write Timings
NWAIT
A
[25:2]
MCK
NRD
There may be a latency between the assertion of the read/write controlling signal and the asser-
tion of the NWAIT signal by the device. The programmed pulse length of the read/write
controlling signal must be at least equal to this latency plus the 2 cycles of resynchronization + 1
cycle. Otherwise, the SMC may enter the hold state of the access without detecting the NWAIT
signal assertion. This is true in frozen mode as well as in ready mode. This is illustrated on
ure
When EXNW_MODE is enabled (ready or frozen), the user must program a pulse length of the
read and write controlling signal of at least:
minimal pulse length = NWAIT latency + 2 resynchronization cycles + 1 cycle
29-30.
4
NWAIT latency
3
2 cycle resynchronization
minimal pulse length
2
EXNW_MODE = 10 or 11
READ_MODE = 1 (NRD_controlled)
NRD_PULSE = 5
Read cycle
1
0
0
WAIT STATE
0
SAM9G25
SAM9G25
Fig-
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414

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