SAM9G25 Atmel Corporation, SAM9G25 Datasheet - Page 490

• Manufacturer Part Number: SAM9G25
• Manufacturer: Atmel Corporation

Specifications of SAM9G25

• Flash (kbytes): 0 Kbytes
• Pin Count: 247
• Max. Operating Frequency: 400 MHz
• Cpu: ARM926
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 105
• Ext Interrupts: 105
• Usb Transceiver: 3
• Usb Speed: Hi-Speed
• Usb Interface: Host, Device
• Spi: 2
• Twi (i2c): 3
• Uart: 7
• Lin: 4
• Ssc: 1
• Ethernet: 1
• Sd / Emmc: 2
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: Yes
• Adc Channels: 12
• Adc Resolution (bits): 10
• Adc Speed (ksps): 440
• Resistive Touch Screen: No
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 32
• Self Program Memory: NO
• External Bus Interface: 1
• Dram Memory: DDR2/LPDDR, SDRAM/LPSDR
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8/3.3
• Operating Voltage (vcc): 0.9 to 1.1
• Fpu: No
• Mpu / Mmu: No/Yes
• Timers: 6
• Output Compare Channels: 6
• Input Capture Channels: 6
• Pwm Channels: 4
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: No

31.4.4.2
Table 31-3.
Notes:
490
490
9) Automatic mode channel
2) Multi Buffer transfer with
3) Multi Buffer transfer with
4) Multi Buffer transfer with
5) Multi Buffer transfer with
6) Multi Buffer transfer with
8) Multi Buffer transfer with
BTSIZE, SADDR reloaded
with BTSIZE reloaded and
buffer of a multiple buffer
and DADDR contiguous
1) Single Buffer or Last
7) Multi Buffer transfer
BTSIZE reloaded and
BTSIZE, SADDR and
Replay Mode of Channel Registers
Contiguous Address Between Buffers
10) Automatic mode
11) Automatic mode
contiguous DADDR
contiguous SADDR
contiguous DADDR
contiguous SADDR
BTsize is reloaded
DADDR reloaded
SADDR reloaded
DADDR reloaded
Transfer Type
LLI support
is stalling
1. USR means that the register field is manually programmed by the user.
2. CONT means that address are contiguous.
3. REP means that the register field is updated with its previous value. If the transfer is the first one, then the user must manu-
4. Channel stalled is true if the relevant BTC interrupt is not masked.
5. LLI means that the register field is updated with the content of the linked list item.
transfer
SAM9G25
SAM9G25
ally program the value.
Programming DMAC for Multiple Buffer Transfers
Multiple Buffers Transfer Management Table
AUTO
0
0
0
0
0
0
1
1
1
1
1
During automatic replay mode, the channel registers are reloaded with their initial values at the
completion of each buffer and the new values used for the new buffer. Depending on the row
number in
DMAC_CTRLAx and DMAC_CTRLBx channel registers are reloaded from their initial value at
the start of a buffer transfer.
In this case, the address between successive buffers is selected to be a continuation from the
end of the previous buffer. Enabling the source or destination address to be contiguous between
SRC_REP
–
–
0
–
–
1
–
0
0
1
1
Table 31-3 on page
DST_REP
–
0
–
–
1
–
0
–
0
1
0
SRC_DSCR
–
0
1
0
0
1
0
1
1
1
1
490, some or all of the DMAC_SADDRx, DMAC_DADDRx,
DST_DSCR
–
1
0
0
1
0
1
0
1
1
1
BTSIZE
USR
REP
REP
REP
REP
REP
LLI
LLI
LLI
LLI
LLI
DSCR
USR
USR
USR
USR
USR
USR
USR
USR
USR
USR
0
SADDR
CONT
CONT
CONT
USR
REP
REP
REP
LLI
LLI
LLI
LLI
DADDR Other Fields
CONT
CONT
CONT
CONT
11032A–ATARM–27-Jul-11
11032A–ATARM–27-Jul-11
USR
REP
REP
LLI
LLI
LLI
LLI
USR
REP
REP
REP
LLI
LLI
LLI
LLI
LLI
LLI
LLI