SAM9G25 Atmel Corporation, SAM9G25 Datasheet - Page 212

• Manufacturer Part Number: SAM9G25
• Manufacturer: Atmel Corporation

Specifications of SAM9G25

• Flash (kbytes): 0 Kbytes
• Pin Count: 247
• Max. Operating Frequency: 400 MHz
• Cpu: ARM926
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 105
• Ext Interrupts: 105
• Usb Transceiver: 3
• Usb Speed: Hi-Speed
• Usb Interface: Host, Device
• Spi: 2
• Twi (i2c): 3
• Uart: 7
• Lin: 4
• Ssc: 1
• Ethernet: 1
• Sd / Emmc: 2
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: Yes
• Adc Channels: 12
• Adc Resolution (bits): 10
• Adc Speed (ksps): 440
• Resistive Touch Screen: No
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 32
• Self Program Memory: NO
• External Bus Interface: 1
• Dram Memory: DDR2/LPDDR, SDRAM/LPSDR
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8/3.3
• Operating Voltage (vcc): 0.9 to 1.1
• Fpu: No
• Mpu / Mmu: No/Yes
• Timers: 6
• Output Compare Channels: 6
• Input Capture Channels: 6
• Pwm Channels: 4
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: No

22.13.11 PMC Master Clock Register
Name:
Address:
Access:
• CSS: Master/Processor Clock Source Selection
• PRES: Master/Processor Clock Prescaler
• MDIV: Master Clock Division
212
212
31
23
15
–
–
–
7
–
Value
Value
Value
0
1
2
3
SAM9G25
SAM9G25
0
1
2
3
0
1
2
3
4
5
6
7
30
22
14
Name
EQ_PCK
PCK_DIV2
PCK_DIV4
PCK_DIV3
PMC_MCKR
0xFFFFFC30
Read-write
–
–
–
6
Name
SLOW_CLK
MAIN_CLK
PLLA_CLK
UPLL_CLK
Name
CLOCK
CLOCK_DIV2
CLOCK_DIV4
CLOCK_DIV8
CLOCK_DIV16
CLOCK_DIV32
CLOCK_DIV64
Reserved
PRES
29
21
13
–
–
–
5
PLLADIV2
Description
Master Clock is Prescaler Output Clock divided by 1.
Warning: SysClk DDR and DDRCK are not available.
Master Clock is Prescaler Output Clock divided by 2.
SysClk DDR is equal to 2 x MCK. DDRCK is equal to MCK.
Master Clock is Prescaler Output Clock divided by 4.
SysClk DDR is equal to 2 x MCK. DDRCK is equal to MCK.
Master Clock is Prescaler Output Clock divided by 3.
SysClk DDR is equal to 2 x MCK. DDRCK is equal to MCK.
28
20
12
–
–
4
Description
Selected clock
Selected clock divided by 2
Selected clock divided by 4
Selected clock divided by 8
Selected clock divided by 16
Selected clock divided by 32
Selected clock divided by 64
Reserved
Description
Slow Clock is selected
Main Clock is selected
PLLACK/PLLADIV2 is selected
UPLL Clock is selected
27
19
11
–
–
–
–
3
26
18
10
–
–
–
2
–
25
17
–
–
9
1
11032A–ATARM–27-Jul-11
11032A–ATARM–27-Jul-11
MDIV
CSS
24
16
–
–
8
0