SAM7X256 Atmel Corporation, SAM7X256 Datasheet - Page 672

• Manufacturer Part Number: SAM7X256
• Manufacturer: Atmel Corporation

Specifications of SAM7X256

• Flash (kbytes): 256 Kbytes
• Pin Count: 100
• Max. Operating Frequency: 55 MHz
• Cpu: ARM7TDMI
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 62
• Ext Interrupts: 62
• Usb Transceiver: 1
• Usb Speed: Full Speed
• Usb Interface: Device
• Spi: 2
• Twi (i2c): 1
• Uart: 3
• Can: 1
• Ssc: 1
• Ethernet: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 8
• Adc Resolution (bits): 10
• Adc Speed (ksps): 384
• Resistive Touch Screen: No
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 64
• Self Program Memory: NO
• Dram Memory: No
• Nand Interface: No
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 3.3
• Operating Voltage (vcc): 3.0 to 3.6
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 3
• Output Compare Channels: 3
• Input Capture Channels: 3
• Pwm Channels: 4
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: No

676
Version
6120G
SAM7X512/256/128
Comments
Overview,
“Features”, TWI updated to include Atmel TWI compatibility with I
Section 7.4 ”Peripheral DMA Controller”
Section 10.8 ”Two-wire
Section 10.11 ”Timer Counter”
Section 10.15 ”Analog-to-Digital Converter”
CAN,
versa have been inverted.
Debug and Test,
Section 12.5.5 ”ID Code
DBGU,
Section 26.5.10 ”Debug Unit Chip ID
“SRAMSIZ: Internal SRAM Size” on page 226
Corrected bin values for 0x60 and 0xF0 and Architecture Identifier bit description for CAP7, AT91SAM7AQxx
Series and CAP11 in the bit description,
EMAC,
Section 37.5.3 “Network Status Register” on page
Section 37.3 “Functional Description” on page
FFPI,
Table
Global update to terms listed below:
Fuse → GPNVM
SFB → SGPB
CFB → CGPB
GFB → GGPB
Section 20.2.5.6 on page 126
PIO,
Section 27.4.5 “Synchronous Data Output” on page
Section 27.6 “Parallel Input/Output Controller (PIO) User Interface” on page
PIO_PSR, PIO_ODSR, PIO_PDSR in Register Mapping table.
PMC,
Section 25.3 ”Processor Clock Controller”
Figure 24-2,”Typical Crystal Connection”
PWM,
Section 33.6 “Pulse Width Modulation Controller (PWM) User Interface” on page
33-2, Register Mapping ; the PWM channel-dependent registers listed as indexed registers.
See
Section 33.6.11 ”PWM Channel Period
Section 33.6.13 ”PWM Channel Update
SPI,
Section 28.6.4 “SPI Slave Mode” on page
SPI_RDR.
Section 33.6.9 ”PWM Channel Mode
Figure 36-7,”Line Error Mode”
20-6,
Table
20-9,
Interface”, updated.
Table 20-18
Register”, product part numbers and JTAG ID code values updated.
&
The TC has Two output compare or one input capture per channel.
Section 20.3.4.6 on page
Conditions to switch from Error Active mode to Error Passive mode and vice
updated
Register”, SRAM bit description added for AT91SAM7L in the bit field.
Register”,
Register”;
updated with PDC priorities.
“ARCH: Architecture Identifier” on page 227
updated, removed C
Register”,
....the processor clock can be disabled by writing.... PMC_SDR.
265, corrected information on OVRES (SPI_SR) and data read in
INL and DNL updated.
562, Added information on clocks in first paragraph.
Section 33.6.12 ”PWM Channel Counter
581, Corrected status for IDLE bit.
234, PIO_OWSR typo corrected.
Section 33.6.10 ”PWM Channel Duty Cycle
133, security bit restraint on access to FFPI explained.
L1
and C
2
C Standard.
L2
labels.
238, 10, footnotes updated on
433, the Offset column in
Register”, and
Register”,
6120I–ATARM–06-Apr-11
Table
Change
Request
Ref.
4247
4774
4210
4007
4089
4382
3828
3369,
3807
3326
3328
4410
3933
4744
3289
3974
3835
3861
4486
3943