SAM7X256 Atmel Corporation, SAM7X256 Datasheet - Page 561

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SAM7X256

Manufacturer Part Number
SAM7X256
Description
Manufacturer
Atmel Corporation
Datasheets

Specifications of SAM7X256

Flash (kbytes)
256 Kbytes
Pin Count
100
Max. Operating Frequency
55 MHz
Cpu
ARM7TDMI
Hardware Qtouch Acquisition
No
Max I/o Pins
62
Ext Interrupts
62
Usb Transceiver
1
Usb Speed
Full Speed
Usb Interface
Device
Spi
2
Twi (i2c)
1
Uart
3
Can
1
Ssc
1
Ethernet
1
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
8
Adc Resolution (bits)
10
Adc Speed (ksps)
384
Resistive Touch Screen
No
Temp. Sensor
No
Crypto Engine
No
Sram (kbytes)
64
Self Program Memory
NO
Dram Memory
No
Nand Interface
No
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
3.3
Operating Voltage (vcc)
3.0 to 3.6
Fpu
No
Mpu / Mmu
no / no
Timers
3
Output Compare Channels
3
Input Capture Channels
3
Pwm Channels
4
32khz Rtc
Yes
Calibrated Rc Oscillator
No
37. Ethernet MAC 10/100 (EMAC)
37.1
37.2
6120I–ATARM–06-Apr-11
Overview
Block Diagram
The EMAC module implements a 10/100 Ethernet MAC compatible with the IEEE 802.3 stan-
dard using an address checker, statistics and control registers, receive and transmit blocks, and
a DMA interface.
The address checker recognizes four specific 48-bit addresses and contains a 64-bit hash regis-
ter for matching multicast and unicast addresses. It can recognize the broadcast address of all
ones, copy all frames, and act on an external address match signal.
The statistics register block contains registers for counting various types of event associated
with transmit and receive operations. These registers, along with the status words stored in the
receive buffer list, enable software to generate network management statistics compatible with
IEEE 802.3.
Figure 37-1.
Slave
APB
Master
ASB
EMAC Block Diagram
RX FIFO
Register Interface
DMA Interface
TX FIFO
Statistics Registers
Control Registers
Address Checker
Ethernet Receive
Ethernet Transmit
SAM7X512/256/128
MII/RMII
MDIO
561

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