SAM7X256 Atmel Corporation, SAM7X256 Datasheet - Page 573

• Manufacturer Part Number: SAM7X256
• Manufacturer: Atmel Corporation

Specifications of SAM7X256

• Flash (kbytes): 256 Kbytes
• Pin Count: 100
• Max. Operating Frequency: 55 MHz
• Cpu: ARM7TDMI
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 62
• Ext Interrupts: 62
• Usb Transceiver: 1
• Usb Speed: Full Speed
• Usb Interface: Device
• Spi: 2
• Twi (i2c): 1
• Uart: 3
• Can: 1
• Ssc: 1
• Ethernet: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 8
• Adc Resolution (bits): 10
• Adc Speed (ksps): 384
• Resistive Touch Screen: No
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 64
• Self Program Memory: NO
• Dram Memory: No
• Nand Interface: No
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 3.3
• Operating Voltage (vcc): 3.0 to 3.6
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 3
• Output Compare Channels: 3
• Input Capture Channels: 3
• Pwm Channels: 4
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: No

37.4
37.4.1
37.4.1.1
37.4.1.2
Figure 37-2. Receive Buffer List
6120I–ATARM–06-Apr-11
Programming Interface
Initialization
Configuration
Receive Buffer List
Receive Buffer Queue Pointer
(MAC Register)
Initialization of the EMAC configuration (e.g., loop-back mode, frequency ratios) must be done
while the transmit and receive circuits are disabled. See the description of the network control
register and network configuration register earlier in this document.
To change loop-back mode, the following sequence of operations must be followed:
Note:
Receive data is written to areas of data (i.e., buffers) in system memory. These buffers are listed
in another data structure that also resides in main memory. This data structure (receive buffer
queue) is a sequence of descriptor entries as defined in
page
To create the list of buffers:
1. Write to network control register to disable transmit and receive circuits.
2. Write to network control register to change loop-back mode.
3. Write to network control register to re-enable transmit or receive circuits.
1. Allocate a number (n) of buffers of 128 bytes in system memory.
2. Allocate an area 2n words for the receive buffer descriptor entry in system memory and
3. If less than 1024 buffers are defined, the last descriptor must be marked with the wrap
4. Write address of receive buffer descriptor entry to EMAC register receive_buffer
5. The receive circuits can then be enabled by writing to the address recognition registers
563. It points to this data structure.
create n entries in this list. Mark all entries in this list as owned by EMAC, i.e., bit 0 of
word 0 set to 0.
bit (bit 1 in word 0 set to 1).
queue pointer.
and then to the network control register.
These writes to network control register cannot be combined in any way.
Receive Buffer Descriptor List
(In memory)
“Receive Buffer Descriptor Entry” on
SAM7X512/256/128
Receive Buffer 1
Receive Buffer 0
Receive Buffer N
(In memory)
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