SAM7X256 Atmel Corporation, SAM7X256 Datasheet - Page 513

• Manufacturer Part Number: SAM7X256
• Manufacturer: Atmel Corporation

Specifications of SAM7X256

• Flash (kbytes): 256 Kbytes
• Pin Count: 100
• Max. Operating Frequency: 55 MHz
• Cpu: ARM7TDMI
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 62
• Ext Interrupts: 62
• Usb Transceiver: 1
• Usb Speed: Full Speed
• Usb Interface: Device
• Spi: 2
• Twi (i2c): 1
• Uart: 3
• Can: 1
• Ssc: 1
• Ethernet: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 8
• Adc Resolution (bits): 10
• Adc Speed (ksps): 384
• Resistive Touch Screen: No
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 64
• Self Program Memory: NO
• Dram Memory: No
• Nand Interface: No
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 3.3
• Operating Voltage (vcc): 3.0 to 3.6
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 3
• Output Compare Channels: 3
• Input Capture Channels: 3
• Pwm Channels: 4
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: No

36.6.4.3
36.6.4.4
6120I–ATARM–06-Apr-11
Autobaud Mode
Error Detection
Figure 36-6. CAN Resynchronization
The autobaud feature is enabled by setting the ABM field in the CAN_MR register. In this mode,
the CAN controller is only listening to the line without acknowledging the received messages. It
can not send any message. The errors flags are updated. The bit timing can be adjusted until no
error occurs (good configuration found). In this mode, the error counters are frozen. To go back
to the standard mode, the ABM bit must be cleared in the CAN_MR register.
There are five different error types that are not mutually exclusive. Each error concerns only spe-
cific fields of the CAN data frame (refer to the Bosch CAN specification for their
correspondence):
• CRC error (CERR bit in the CAN_SR register): With the CRC, the transmitter calculates a
• Bit-stuffing error (SERR bit in the CAN_SR register): If a node detects a sixth consecutive
• Bit error (BERR bit in CAN_SR register): A bit error occurs if a transmitter sends a dominant
• Form Error (FERR bit in the CAN_SR register): If a transmitter detects a dominant bit in one
checksum for the CRC bit sequence from the Start of Frame bit until the end of the Data
Field. This CRC sequence is transmitted in the CRC field of the Data or Remote Frame.
equal bit level during the bit-stuffing area of a frame, it generates an Error Frame starting with
the next bit-time.
bit but detects a recessive bit on the bus line, or if it sends a recessive bit but detects a
dominant bit on the bus line. An error frame is generated and starts with the next bit time.
of the fix-formatted segments CRC Delimiter, ACK Delimiter or End of Frame, a form error
has occurred and an error frame is generated.
(before resynchronization)
(before resynchronization)
resynchronization
resynchronization
Nominal bit time
Nominal bit time
Bit time with
Bit time with
Received
Received
data bit
data bit
THE PHASE ERROR IS POSITIVE
(the transmitter is slower than the receiver)
THE PHASE ERROR IS NEGATIVE
(the transmitter is faster than the receiver)
SYNC_
SYNC_
SEG
SEG
PHASE_
PHASE_SEG2
Phase error
SEG2
Phase error
Phase error (max Tsjw)
PROP_SEG
PROP_SEG
SYNC_
SEG
SYNC_
SEG
PROP_SEG
PHASE_SEG1 PHASE_SEG2
PHASE_SEG1
PROP_SEG
Sample point
Nominal
after resynchronization
Phase error (max Tsjw)
PHASE_SEG1
SAM7X512/256/128
Sample point
Sample point
after resynchronization
PHASE_SEG2
PHASE_SEG1
SYNC_
PHASE_SEG2
SEG
Nominal
Sample point
PHASE_SEG2
SYNC_
SEG
SYNC_
SEG
SYNC_
SEG
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