SAM7X256 Atmel Corporation, SAM7X256 Datasheet - Page 111

• Manufacturer Part Number: SAM7X256
• Manufacturer: Atmel Corporation

Specifications of SAM7X256

• Flash (kbytes): 256 Kbytes
• Pin Count: 100
• Max. Operating Frequency: 55 MHz
• Cpu: ARM7TDMI
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 62
• Ext Interrupts: 62
• Usb Transceiver: 1
• Usb Speed: Full Speed
• Usb Interface: Device
• Spi: 2
• Twi (i2c): 1
• Uart: 3
• Can: 1
• Ssc: 1
• Ethernet: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 8
• Adc Resolution (bits): 10
• Adc Speed (ksps): 384
• Resistive Touch Screen: No
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 64
• Self Program Memory: NO
• Dram Memory: No
• Nand Interface: No
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 3.3
• Operating Voltage (vcc): 3.0 to 3.6
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 3
• Output Compare Channels: 3
• Input Capture Channels: 3
• Pwm Channels: 4
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: No

19.2.4.4
19.2.4.5
6120I–ATARM–06-Apr-11
General-purpose NVM Bits
Security Bit
General-purpose NVM bits do not interfere with the embedded Flash memory plane. (Does not
apply to EFC1 on the AT91SAM7X512.) These general-purpose bits are dedicated to protect
other parts of the product. They can be set (activated) or cleared individually. Refer to the prod-
uct definition section for the general-purpose NVM bit action.
The activation sequence is:
Two errors can be detected in the MC_FSR register after a programming sequence:
It is possible to deactivate a general-purpose NVM bit set previously. The clear sequence is:
Two errors can be detected in the MC_FSR register after a programming sequence:
The Clear General-purpose Bit command programs the general-purpose NVM bit to 0; the corre-
sponding bit GPNVM0 to GPNVMx in MC_FSR reads 0. The Set General-purpose Bit command
programs the general-purpose NVM bit to 1; the corresponding bit GPNVMx in MC_FSR reads 1.
Note:
The goal of the security bit is to prevent external access to the internal bus system. (Does not
apply to EFC1 on the AT91SAM7X512.) JTAG, Fast Flash Programming and Flash Serial Test
Interface features are disabled. Once set, this bit can be reset only by an external hardware
ERASE request to the chip. Refer to the product definition section for the pin name that controls
the ERASE. In this case, the full memory plane is erased and all lock and general-purpose NVM
bits are cleared. The security bit in the MC_FSR is cleared only after these operations. The acti-
vation sequence is:
• Start the Set General Purpose Bit command (SGPB) by writing the Flash Command Register
• When the bit is set, the bit FRDY in the Flash Programming Status Register (MC_FSR) rises.
• Programming Error: A bad keyword and/or an invalid command have been written in the
• If the general-purpose bit number is greater than the total number of general-purpose bits,
• Start the Clear General-purpose Bit command (CGPB) by writing the Flash Command
• When the clear completes, the bit FRDY in the Flash Programming Status Register
• Programming Error: a bad keyword and/or an invalid command have been written in the
• If the number of the general-purpose bit set in the PAGEN field is greater than the total
• Start the Set Security Bit command (SSB) by writing the Flash Command Register.
with the SEL command and the number of the general-purpose bit to be set in the PAGEN
field.
If an interrupt has been enabled by setting the bit FRDY in MC_FMR, the interrupt line of the
Memory Controller is activated.
MC_FCR register
then the command has no effect.
Register with CGPB and the number of the general-purpose bit to be cleared in the PAGEN
field.
(MC_FSR) rises. If an interrupt has been enabled by setting the bit FRDY in MC_FMR, the
interrupt line of the Memory Controller is activated.
MC_FCR register
number of general-purpose bits, then the command has no effect.
Access to the Flash in read mode is permitted when a Set, Clear or Get General-purpose NVM Bit
command is performed.
SAM7X512/256/128
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