SAM7X256 Atmel Corporation, SAM7X256 Datasheet - Page 545

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SAM7X256

Manufacturer Part Number
SAM7X256
Description
Manufacturer
Atmel Corporation
Datasheets

Specifications of SAM7X256

Flash (kbytes)
256 Kbytes
Pin Count
100
Max. Operating Frequency
55 MHz
Cpu
ARM7TDMI
Hardware Qtouch Acquisition
No
Max I/o Pins
62
Ext Interrupts
62
Usb Transceiver
1
Usb Speed
Full Speed
Usb Interface
Device
Spi
2
Twi (i2c)
1
Uart
3
Can
1
Ssc
1
Ethernet
1
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
8
Adc Resolution (bits)
10
Adc Speed (ksps)
384
Resistive Touch Screen
No
Temp. Sensor
No
Crypto Engine
No
Sram (kbytes)
64
Self Program Memory
NO
Dram Memory
No
Nand Interface
No
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
3.3
Operating Voltage (vcc)
3.0 to 3.6
Fpu
No
Mpu / Mmu
no / no
Timers
3
Output Compare Channels
3
Input Capture Channels
3
Pwm Channels
4
32khz Rtc
Yes
Calibrated Rc Oscillator
No
36.8.8
Name:
Access Type:
• MTIMESTAMPx: Timestamp
This field represents the internal CAN controller 16-bit timer value.
If the TEOF bit is cleared in the CAN_MR register, the internal Timer Counter value is captured in the MTIMESTAMP field
at each start of frame. Else the value is captured at each end of frame. When the value is captured, the TSTP flag is set in
the CAN_SR register. If the TSTP mask in the CAN_IMR register is set, an interrupt is generated while TSTP flag is set in
the CAN_SR register. This flag is cleared by reading the CAN_SR register.
Note:
6120I–ATARM–06-Apr-11
MTIMESTAMP15 MTIMESTAMP14 MTIMESTAMP13 MTIMESTAMP12 MTIMESTAMP11 MTIMESTAMP10
MTIMESTAMP7
31
23
15
7
The CAN_TIMESTP register is reset when the CAN is disabled then enabled thanks to the CANEN bit in the CAN_MR.
CAN Timestamp Register
MTIMESTAMP6
30
22
14
CAN_TIMESTP
Read-only
6
MTIMESTAMP5
29
21
13
5
MTIMESTAMP4
28
20
12
4
MTIMESTAMP3
27
19
11
3
MTIMESTAMP2
26
18
10
2
SAM7X512/256/128
MTIMESTAMP9
MTIMESTAMP1
25
17
9
1
MTIMESTAMP8
MTIMESTAMP0
24
16
8
0
545

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