SAM7X256 Atmel Corporation, SAM7X256 Datasheet - Page 640

• Manufacturer Part Number: SAM7X256
• Manufacturer: Atmel Corporation

Specifications of SAM7X256

• Flash (kbytes): 256 Kbytes
• Pin Count: 100
• Max. Operating Frequency: 55 MHz
• Cpu: ARM7TDMI
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 62
• Ext Interrupts: 62
• Usb Transceiver: 1
• Usb Speed: Full Speed
• Usb Interface: Device
• Spi: 2
• Twi (i2c): 1
• Uart: 3
• Can: 1
• Ssc: 1
• Ethernet: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 8
• Adc Resolution (bits): 10
• Adc Speed (ksps): 384
• Resistive Touch Screen: No
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 64
• Self Program Memory: NO
• Dram Memory: No
• Nand Interface: No
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 3.3
• Operating Voltage (vcc): 3.0 to 3.6
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 3
• Output Compare Channels: 3
• Input Capture Channels: 3
• Pwm Channels: 4
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: No

41.3.2
41.3.2.1
41.3.2.2
41.3.3
41.3.3.1
41.3.3.2
41.3.3.3
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SAM7X512/256/128
Controller Area Network (CAN)
Ethernet MAC (EMAC)
CAN: Low Power Mode and Error Frame
CAN: Low Power Mode and Pending Transmit Messages
EMAC: RMII Mode
EMAC: Possible Event Loss when Reading EMAC_ISR
EMAC: Possible Event Loss when Reading the Statistics Register Block
To activate sleep mode as soon as possible, it is recommended to write successively, ADC
Mode Register (SLEEP) then ADC Control Register (START bit field); to start an analog-to-digi-
tal conversion, in order put ADC into sleep mode at the end of this conversion.
If the Low Power Mode is activated while the CAN is generating an error frame, this error frame
may be shortened.
None
No pending transmit messages may be sent once the CAN Controller enters Low-power Mode.
Check that all messages have been sent by reading the related Flags before entering Low-
power Mode.
RMII mode is not functional.
None
If an event occurs within the same clock cycle in which the EMAC_ISR is read, the correspond-
ing bit might be cleared even though it has not been read at 1. This might lead to the loss of this
event.
Each time the software reads EMAC_ISR, it has to check the contents of the Transmit Status
Register (EMAC_TSR), the Receive Status Register (EMAC_RSR) and the Network Status
Register (EMAC_NSR), as the possible lost event is still notified in one of these registers.
If an event occurs within the same clock cycle during which a statistics register is read, the cor-
responding counter might lose this event. This might lead to the loss of the incrementation of
one for this counter.
None
Problem Fix/Workaround
Problem Fix/Workaround
Problem Fix/Workaround
Problem Fix/Workaround
Problem Fix/Workaround
6120I–ATARM–06-Apr-11