PEB 20542 F V1.3 Infineon Technologies, PEB 20542 F V1.3 Datasheet - Page 99

• Manufacturer Part Number: PEB 20542 F V1.3
• Description: IC CTRLR DMA SERIAL 2-CH TQFP144
• Manufacturer: Infineon Technologies
• Series: SEROCCO™r

Specifications of PEB 20542 F V1.3

• Function: Serial Optimized Communications Controller
• Interface: HDLC, PPP
• Number Of Circuits: 2
• Voltage - Supply: 3 V ~ 3.6 V
• Current - Supply: 50mA
• Power (watts): 150mW
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 144-LFQFP
• Includes: Bit Processor Functions, Serial Communication Controllers (SCCs)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: PEB20542FV1.3X; SP000007633

4.3
Characteristics: fully transparent
When programmed in the extended transparent mode via the
MDS1, MDS0, ADM = ‘111’), the SCC performs fully transparent data transmission and
reception without HDLC framing, i.e. without
• FLAG insertion and deletion
• CRC generation and checking
• bit stuffing.
This feature can be profitably used e.g. for:
• user specific protocol variations
• line state monitoring, or
• test purposes, in particular for monitoring or intentionally generating HDLC protocol
Character or octet boundary synchronization can be achieved by using clock mode 5 or
clock mode 1 with an external receive strobe input to pin CD.
Note: Data is transmitted and received with the least significant bit (LSB) first.
4.4
4.4.1
Character framing is achieved by start and stop bits. Each data character is preceded by
one Start bit and terminated by one or two stop bits. The character length is selectable
from 5 up to 8 bits. Optionally, a parity bit can be added which complements the number
of ones to an even or odd quantity (even/odd parity). The parity bit can also be
programmed to have a fixed value (Mark or Space). The character format configuration
is performed via appropriate bit fields in registers CCR3L/CCR3H.
asynchronous character format.
Data Sheet
rule violations (e.g. wrong CRC)
Extended Transparent Mode
Asynchronous (ASYNC) Protocol Mode
Character Framing
99
Detailed Protocol Description
CCR2L
Figure 49
register (bits
PEB 20542
PEF 20542
2000-09-14
shows the