PEB 20542 F V1.3 Infineon Technologies, PEB 20542 F V1.3 Datasheet - Page 236

• Manufacturer Part Number: PEB 20542 F V1.3
• Description: IC CTRLR DMA SERIAL 2-CH TQFP144
• Manufacturer: Infineon Technologies
• Series: SEROCCO™r

Specifications of PEB 20542 F V1.3

• Function: Serial Optimized Communications Controller
• Interface: HDLC, PPP
• Number Of Circuits: 2
• Voltage - Supply: 3 V ~ 3.6 V
• Current - Supply: 50mA
• Power (watts): 150mW
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 144-LFQFP
• Includes: Bit Processor Functions, Serial Communication Controllers (SCCs)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: PEB20542FV1.3X; SP000007633

Data Sheet
C/R
LA
P
’1’
FE
’1’
PE
’1’
Command/Response
Significant only if 2-byte address mode has been selected.
Value of the C/R bit (bit 1 of high address byte) in the received frame.
The interpretation depends on the setting of the ’CRI’ bit in the
register (See “RAH1” on page 207.).
Low Byte Address Compare
Significant in automode and address mode 2 only.
The low byte address of a 2-byte address field, or the single address byte
of a 1-byte address field is compared with two addresses (RAL1, RAL2).
LA=’0’
LA=’1’
According to the X.25 LAPB protocol,
of a COMMAND frame and
RESPONSE frame.
Parity
This bit carries the parity bit of the last received character.
Framing Error
A character framing error was detected, i.e. a ’0’ was sampled at a bit
position where a stop bit ’1’ was expected due to the selected character
format.
Parity Error
The calculated parity did not match the received parity bit. Optionally the
interrupt PERR can be generated.
RAL2
RAL1
has been recognized.
has been recognized.
236
RAL2
is interpreted as the address of a
RAL1
is interpreted as the address
Register Description
(async/bisync mode)
(async/bisync mode)
(async mode)
(hdlc modes)
(hdlc modes)
PEB 20542
PEF 20542
2000-09-14
RAH1