PEB 20542 F V1.3 Infineon Technologies, PEB 20542 F V1.3 Datasheet - Page 214

• Manufacturer Part Number: PEB 20542 F V1.3
• Description: IC CTRLR DMA SERIAL 2-CH TQFP144
• Manufacturer: Infineon Technologies
• Series: SEROCCO™r

Specifications of PEB 20542 F V1.3

• Function: Serial Optimized Communications Controller
• Interface: HDLC, PPP
• Number Of Circuits: 2
• Voltage - Supply: 3 V ~ 3.6 V
• Current - Supply: 50mA
• Power (watts): 150mW
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 144-LFQFP
• Includes: Bit Processor Functions, Serial Communication Controllers (SCCs)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: PEB20542FV1.3X; SP000007633

Data Sheet
RCE
RL(10:0)
Receive Length Check Enable
This bit is valid in HDLC mode only and enables/disables the receive
length check function:
RCE = ’0’
RCE = ’1’
Receive Length Check Limit
This bit-field defines the receive length check limit (32..65536 bytes) if
checking is enabled via bit ’RCE’:
RL(10:0)
No receive length check on received HDLC frames is
performed.
The receive length check is enabled. All bytes of a HDLC
frame which are transferred to the receive FIFO
(depending on the selected protocol sub-mode and
receive CRC handling) are counted and checked against
the maximum length check limit which is programmed in
bit field ’RL’.
A frame exceeding the maximum length is treated as if it
were aborted on the receive line (’RME’ interrupt and bit
’RAB’ (receive abort) set in the
In addition a ’FLEX’ interrupt is generated prior to ’RME’,
if enabled.
Note: The Receive Status Byte (RSTA) is part of the
The receive length limit is calculated by:
frame length checking.
5-214
Limit
=
Register Description (RLCRH)
(
RL
+
RSTA
1
) 32
×
byte).
(hdlc modes)
(hdlc modes)
PEB 20542
PEF 20542
2000-09-14