PEB 20542 F V1.3 Infineon Technologies, PEB 20542 F V1.3 Datasheet - Page 270

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PEB 20542 F V1.3

Manufacturer Part Number
PEB 20542 F V1.3
Description
IC CTRLR DMA SERIAL 2-CH TQFP144
Manufacturer
Infineon Technologies
Series
SEROCCO™r
Datasheet

Specifications of PEB 20542 F V1.3

Function
Serial Optimized Communications Controller
Interface
HDLC, PPP
Number Of Circuits
2
Voltage - Supply
3 V ~ 3.6 V
Current - Supply
50mA
Power (watts)
150mW
Operating Temperature
0°C ~ 70°C
Mounting Type
Surface Mount
Package / Case
144-LFQFP
Includes
Bit Processor Functions, Serial Communication Controllers (SCCs)
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
PEB20542FV1.3X
SP000007633
The data reception flow, from the CPU’s point of view, is outlined in
Figure 67
6.3.3
In buffer switched mode, operation will be similar but the DMA controller will
autonomously switch between buffer base addresses TBADDR1/RBADDR1 and
TBADDR2/RBADDR2 after any buffer completion.
Data Sheet
The end of the packet is not
contained in this RxBuffer.
controller filled the current
RxBuffer to the maximum
indicates that the DMA
level (<RMBS> bytes).
The 'RBF' interrupt
Buffer Switched Mode
DMA Controlled Data Reception (Flow Diagram)
Interrupt
'RBF'
of current RxBuffer
(RBADDR1H/M/L)
Size ('RMBS') and
Set Base Address
RX DMA ACTIVE
register GMODE)
RX DMA READY
(set bit 'IDMA' in
('RE') in register
Enable Receive
Set Max Buffer
Enable DMA
RMBSL/H
START
270
(CMDRH.RMC)
Release RFIFO
Read Receive
Byte Count
(RBCL/H)
Interrupt
'RDTE'
Action taken by
CPU
Interrupt
indication to CPU
indicates that the end of the
packet currently received is
Figure
contained in the current
The 'RDTE' interrupt
Programming
RxBuffer.
PEB 20542
PEF 20542
67.
2000-09-14

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