PEB 20542 F V1.3 Infineon Technologies, PEB 20542 F V1.3 Datasheet - Page 118

• Manufacturer Part Number: PEB 20542 F V1.3
• Description: IC CTRLR DMA SERIAL 2-CH TQFP144
• Manufacturer: Infineon Technologies
• Series: SEROCCO™r

Specifications of PEB 20542 F V1.3

• Function: Serial Optimized Communications Controller
• Interface: HDLC, PPP
• Number Of Circuits: 2
• Voltage - Supply: 3 V ~ 3.6 V
• Current - Supply: 50mA
• Power (watts): 150mW
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 144-LFQFP
• Includes: Bit Processor Functions, Serial Communication Controllers (SCCs)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: PEB20542FV1.3X; SP000007633

Receive
The SS7 protocol is supported by the following hardware features in receive direction:
• Recognition of Signaling Unit type
• Discard of repeatedly received FISUs and optionally of LSSUs if content is unchanged
• Check if the length of the received signaling unit is at least six octets (including the
• Check if the signal information field of a received signaling unit consists of more than
• Counting and processing of errored signaling units
In order to reduce the microprocessor load, Fill In Signaling Units (FISUs) are processed
automatically. By examining the length indicator of a received Signal Unit (SU)
SEROCCO-D decides whether a FISU has been received. Consecutively received
FISUs will be compared and not stored in the RFIFO, if the content is equal to the
previous one. The same applies to Link Status Signaling Units (LSSUs), if enabled with
bit CCR3L.CSF. The different types of Signaling Units as Message Signaling Unit
(MSU), Link Status Signaling Unit (LSSU) and Fill-In Signaling Units (FISU) are indicated
in the
received Signaling Unit. The complete Signaling Unit except start and end flags is stored
in the receive FIFO. The functions of bits CCR3H.RCRC and CCR3H.RADD are also
valid in SS7 mode, with bit ’RADD’ related to BSN (backward sequence number) and
FSN (forward sequence number).
Errored signaling units are counted and processed according to ITU-T Q.703. The SU
counter and errored-SU counter are reset by setting CMDRH.RSUC to ’1’. The error
threshold can be selected to be 64 (default) or 32 by clearing/setting bit CCR3L.SUET.
If the defined error limit is exceeded, an interrupt (ISR1.SUEX) is generated, if not
masked by bit IMR1.SUEX.
Transmit
In transmit direction, following features are supported:
• single or repetitive transmission of signaling units
• automatic generation of Fill-In Signaling Units (FISU)
Each Signaling Unit (SU) written to the transmit FIFO (XFIFO) will be sent once or
repeatedly including flags, CRC checksum and stuffed bits. After e.g. an MSU has been
transmitted completely, SEROCCO-D optionally starts sending of Fill In Signaling Units
(FISUs) containing the forward sequence number (FSN) and the backward sequence
number (BSN) of the previously transmitted signaling unit. Setting bit CCR3L.AFX to ’1’
causes FISUs to be sent continuously if no Signaling Unit is to be transmitted from
XFIFO. After a new signaling unit has been written to the XFIFO and a transmission has
been initiated, the current FISU is completed and the new SU is sent. After this,
Data Sheet
opening flag)
272 octets (enabled with bit CCR3L.ELC). In this case, reception of the current
signaling unit will be aborted.
RSTA
byte (bit field ’SU’), which is automatically added to the RFIFO with each
118
Detailed Protocol Description
PEB 20542
PEF 20542
2000-09-14