PEB 20542 F V1.3 Infineon Technologies, PEB 20542 F V1.3 Datasheet - Page 262

• Manufacturer Part Number: PEB 20542 F V1.3
• Description: IC CTRLR DMA SERIAL 2-CH TQFP144
• Manufacturer: Infineon Technologies
• Series: SEROCCO™r

Specifications of PEB 20542 F V1.3

• Function: Serial Optimized Communications Controller
• Interface: HDLC, PPP
• Number Of Circuits: 2
• Voltage - Supply: 3 V ~ 3.6 V
• Current - Supply: 50mA
• Power (watts): 150mW
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 144-LFQFP
• Includes: Bit Processor Functions, Serial Communication Controllers (SCCs)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: PEB20542FV1.3X; SP000007633

1) A receive threshold of 32 bytes is the default for HDLC/PPP mode. It can be programmed with bit field
2) The number of bytes stored in RFIFO can be determined by evaluating the lower bits in register
Figure 60
Data Sheet
RFTH(1:0) in register CCR3H.
(depending on the selected receive threshold RFTH(1:0)).
Interrupt Driven Data Reception (Flow Diagram)
bytes from RFIFO
Interrupt
'RPF'
Read
[32]
1)
Activate Receiver
(CMDRH.RRES)
Release RFIFO
(CMDRH.RMC)
Reset Receiver
(CCR3L.RAC)
INTERRUPT
WAIT FOR
START
262
bytes from RFIFO
(Rc Byte Count)
Read registers
RBCL, RBCH
[RBCL % 32]
'RME'/'TCD'
Interrupt
Read
1), 2)
Action taken
by CPU
Interrupt
indication to CPU
Programming
PEB 20542
PEF 20542
2000-09-14
RBCL