PEB 20542 F V1.3 Infineon Technologies, PEB 20542 F V1.3 Datasheet - Page 20

• Manufacturer Part Number: PEB 20542 F V1.3
• Description: IC CTRLR DMA SERIAL 2-CH TQFP144
• Manufacturer: Infineon Technologies
• Series: SEROCCO™r

Specifications of PEB 20542 F V1.3

• Function: Serial Optimized Communications Controller
• Interface: HDLC, PPP
• Number Of Circuits: 2
• Voltage - Supply: 3 V ~ 3.6 V
• Current - Supply: 50mA
• Power (watts): 150mW
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 144-LFQFP
• Includes: Bit Processor Functions, Serial Communication Controllers (SCCs)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: PEB20542FV1.3X; SP000007633

• Bit Synchronous PPP Mode
• Octet Synchronous PPP Mode
• Asynchronous PPP Mode
• Asynchronous (ASYNC) Protocol Mode
• BISYNC Protocol Mode
• Extended Transparent Mode
Data Sheet
– CRC generation and checking (CRC-CCITT or CRC-32)
– Transparent CRC option per channel and/or per frame
– Programmable Preamble (8 bit) with selectable repetition rate
– Error detection (abort, long frame, CRC error, short frames)
– Bit oriented transmission of HDLC frame (flag, data, CRC, flag)
– Zero bit insertion/deletion
– 15 consecutive ’1’ bits abort sequence
– Octet oriented transmission of HDLC frame (flag, data, CRC, flag)
– Programmable character map of 32 hard-wired characters (00
– Four programmable characters for additional mapping
– Insertion/deletion of control-escape character (7D
– Character oriented transmission of HDLC frame (flag, data, CRC, flag)
– Start/stop bit framing of single character
– Programmable character map of 32 hard-wired characters (00
– Four programmable characters for additional mapping
– Insertion/deletion of control-escape character (7D
– Selectable character length (5 to 8 bits)
– Even, odd, forced or no parity generation/checking
– 1 or 2 stop bits
– Break detection/generation
– In-band flow control by XON/XOFF
– Immediate character insertion
– Termination character detection for end of block identification
– Time out detection
– Error detection (parity error, framing error)
– Programmable 6/8 bit SYN pattern (MONOSYNC)
– Programmable 12/16 bit SYN pattern (BISYNC)
– Selectable character length (5 to 8 bits)
– Even, odd, forced or no parity generation/checking
– Generation of interframe-time fill ’1’s or SYN characters
– CRC generation (CRC-16 or CRC-CCITT)
– Transparent CRC option per channel and/or per frame
– Programmable Preamble (8 bit) with selectable repetition rate
– Termination character detection for end of block identification
– Error detection (parity error, framing error)
– Fully bit transparent (no framing, no bit manipulation)
– Octet-aligned transmission and reception
20
H
H
) for mapped characters
) for mapped characters
H
H
-1F
-1F
H
H
)
)
Introduction
PEB 20542
PEF 20542
2000-09-14