PEB 20542 F V1.3 Infineon Technologies, PEB 20542 F V1.3 Datasheet - Page 120

• Manufacturer Part Number: PEB 20542 F V1.3
• Description: IC CTRLR DMA SERIAL 2-CH TQFP144
• Manufacturer: Infineon Technologies
• Series: SEROCCO™r

Specifications of PEB 20542 F V1.3

• Function: Serial Optimized Communications Controller
• Interface: HDLC, PPP
• Number Of Circuits: 2
• Voltage - Supply: 3 V ~ 3.6 V
• Current - Supply: 50mA
• Power (watts): 150mW
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 144-LFQFP
• Includes: Bit Processor Functions, Serial Communication Controllers (SCCs)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: PEB20542FV1.3X; SP000007633

5
5.1
The SEROCCO-D global registers are used to configure and control the Serial
Communication Controllers (SCCs), General Purpose Pins (GPP) and DMA operation.
All registers are 8-bit organized registers, but grouped and optimized for 16 bit access.
16 bit access is supported to even addresses only.
Table 15
Table 15
Offset Ch
Global registers:
00
01
02
03
04
05
06
07
08
09
0A
0B
0C
0D
0E
0F
Channel specific registers:
10
11
Data Sheet
A
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
60
61
B
H
H
provides an overview about all on-chip registers:
Register Description
Register Overview
GSTAR
RFIFO
GPIS
DISR
read
Register Overview
Reserved
Reserved
Reserved
Reserved
Register
GCMDR
GMODE
DCMDR
DMODE
GPDAT
GPDIR
DBSR
GPIM
DIMR
XFIFO
write
Res
00
0B
00
00
FF
-
FF
00
00
00
00
77
-
-
Val
H
H
H
H
H
H
H
H
H
H
H
Global Command Register
Global Mode Register
DMA Buffer Status Register
Global Status Register
GPP Direction Register
GPP Data Register
GPP Interrupt Mask Register
GPP Interrupt Status Register
DMA Command Register
DMA Mode Register
DMA Interrupt Status Register
DMA Interrupt Mask Register
Receive/Transmit FIFO (Low Byte)
Receive/Transmit FIFO (High Byte)
120
Meaning
Register Description
PEB 20542
PEF 20542
2000-09-14
126
127
130
131
133
134
135
136
137
139
140
142
143
143
Page