PEB 20542 F V1.3 Infineon Technologies, PEB 20542 F V1.3 Datasheet - Page 127

• Manufacturer Part Number: PEB 20542 F V1.3
• Description: IC CTRLR DMA SERIAL 2-CH TQFP144
• Manufacturer: Infineon Technologies
• Series: SEROCCO™r

Specifications of PEB 20542 F V1.3

• Function: Serial Optimized Communications Controller
• Interface: HDLC, PPP
• Number Of Circuits: 2
• Voltage - Supply: 3 V ~ 3.6 V
• Current - Supply: 50mA
• Power (watts): 150mW
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 144-LFQFP
• Includes: Bit Processor Functions, Serial Communication Controllers (SCCs)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: PEB20542FV1.3X; SP000007633

Data Sheet
Register 2
CPU Accessibility:
Reset Value:
Offset Address:
typical usage:
IDMA
IPC(1:0)
Bit
IDMA
7
Enable Internal DMA
This bit field controls the DMA operation mode:
IDMA=’0’
IDMA=’1’
Interrupt Pin Characteristic
These bits control the characteristic of interrupt output pin INT/INT:
IPC(1:0)
’00’
’01’
’10’
’11’
GMODE
Global Mode Register
6
0
read/write
0B
01
written by CPU
evaluated by SEROCCO-D
H
H
The internal DMA controller functions are disabled.
SEROCCO-D is operated in standard register access
controlled mode.
The internal DMA controller is enabled.
Single Buffer or Switched Buffer operation mode is
selected with register DMODE.
Output Function:
Open Drain active low
Push/Pull active low
Reserved.
Push/Pull active high
5
IPC(1:0)
DMA and Global Control
5-127
4
OSCPD
3
Register Description (GMODE)
BRC
2
DSHP
1
PEB 20542
PEF 20542
2000-09-14
GIM
0