PEB 20542 F V1.3 Infineon Technologies, PEB 20542 F V1.3 Datasheet - Page 102

• Manufacturer Part Number: PEB 20542 F V1.3
• Description: IC CTRLR DMA SERIAL 2-CH TQFP144
• Manufacturer: Infineon Technologies
• Series: SEROCCO™r

Specifications of PEB 20542 F V1.3

• Function: Serial Optimized Communications Controller
• Interface: HDLC, PPP
• Number Of Circuits: 2
• Voltage - Supply: 3 V ~ 3.6 V
• Current - Supply: 50mA
• Power (watts): 150mW
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 144-LFQFP
• Includes: Bit Processor Functions, Serial Communication Controllers (SCCs)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: PEB20542FV1.3X; SP000007633

Additionally, the CTS signal may be used to control data transmission.
4.4.4
4.4.4.1
Break generation:
On issuing the transmit break command (bit ’XBRK’ in register CCR3L), the TxD pin is
immediately forced to physical ‘0’ level with the next following transmit clock edge, and
released with the first transmit clock edge after this command is reset again by software.
Break detection:
The SCC recognizes the break condition upon receiving consecutive (physical) ‘0’s for
the defined character length, the optional parity and the selected number of stop bits
(‘zero’ character and framing error). The ‘zero’ character is not pushed to RFIFO. If
enabled, the ’Break’ interrupt (BRK) is generated.
The break condition will be present until a ‘1’ is received which is indicated by the ‘Break
Terminated’ interrupt (BRKT).
4.4.4.2
Programmable XON and XOFF characters:
The
characters. The number of significant bits in a register is determined by the programmed
character length via bit field ’CHL’ in register
Additionally, two programmable eight-bit values in registers
as masks for the characters XON and XOFF, respectively:
A ‘1’ in any mask bit position has the effect that no comparison is performed between the
corresponding bits in the received characters (‘don’t cares’) and the XON/XOFF value.
At RESET, the masks are zero’ed, i.e. all bit positions will be compared.
A received character is considered to be recognized as a valid XON or XOFF character
– if it is correctly framed (correct length),
– if its bits match the ones in the
– if it has correct parity (if applicable).
Received XON and XOFF characters are stored in the SCC receive FIFO, as any other
characters, when bit ’DXS’ is set to ’0’ in register
in the receive FIFO.
Data Sheet
length,
XON
/
XOFF
Special Functions
Break Detection/Generation
In-band Flow Control by XON/XOFF Characters
registers contain the programmable values for XON and XOFF
XON
or
XOFF
102
CCR3L
registers over the programmed character
CCR3L
.
Detailed Protocol Description
. Otherwise they are not stored
MXON
and
MXOFF
PEB 20542
PEF 20542
2000-09-14
serve