PEB 20542 F V1.3 Infineon Technologies, PEB 20542 F V1.3 Datasheet - Page 153

• Manufacturer Part Number: PEB 20542 F V1.3
• Description: IC CTRLR DMA SERIAL 2-CH TQFP144
• Manufacturer: Infineon Technologies
• Series: SEROCCO™r

Specifications of PEB 20542 F V1.3

• Function: Serial Optimized Communications Controller
• Interface: HDLC, PPP
• Number Of Circuits: 2
• Voltage - Supply: 3 V ~ 3.6 V
• Current - Supply: 50mA
• Power (watts): 150mW
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 144-LFQFP
• Includes: Bit Processor Functions, Serial Communication Controllers (SCCs)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: PEB20542FV1.3X; SP000007633

Data Sheet
XME
XREP
RMC
RNR
RSUC
Transmit Message End
Self-clearing command bit:
XME=’1’
Transmission Repeat Command
Self-clearing command bit:
XREP=’1’
Receive Message Complete
Self-clearing command bit:
RMC=’1’
Receiver Not Ready Command
NON self-clearing command bit:
This command bit is significant in HDLC Automode only.
RNR=’0’
RNR=’1’
Reset Signaling Unit Counter
Self-clearing command bit:
This command bit is significant if HDLC SS7 mode is selected.
RSUC=’1’
Indicates that the data block written last to the XFIFO
contains the end of the packet. This bit should always be
set in conjunction with a transmit command (’XF’ or ’XIF’).
If bit ’XREP’ is set together with bit ’XME’ and ’XF’,
SEROCCO-D repeatedly transmits the contents of the
XFIFO (1..32 bytes).
The cyclic transmission can be stopped with the ’XRES’
command.
With this bit the CPU indicates to SEROCCO-D that the
current receive data has been fetched out of the RFIFO.
Thus the corresponding space in the RFIFO can be
released and re-used by SEROCCO-D for further
incoming data.
Forces the receiver to enter its ’receiver-ready’ state. The
receiver acknowledges received poll or I-Frames with a
’receiver-ready’ indication.
Forces the receiver to enter its ’receiver-not-ready’ state.
The receiver acknowledges received poll or I-Frames with
a ’receiver-not-ready’ indication.
The Signaling System #7 (SS7) unit counter is reset.
5-153
Register Description (CMDRH)
(hdlc/bisync modes)
PEB 20542
PEF 20542
(hdlc mode)
(hdlc mode)
(hdlc mode)
(all modes)
2000-09-14