PEB 20542 F V1.3 Infineon Technologies, PEB 20542 F V1.3 Datasheet - Page 261

• Manufacturer Part Number: PEB 20542 F V1.3
• Description: IC CTRLR DMA SERIAL 2-CH TQFP144
• Manufacturer: Infineon Technologies
• Series: SEROCCO™r

Specifications of PEB 20542 F V1.3

• Function: Serial Optimized Communications Controller
• Interface: HDLC, PPP
• Number Of Circuits: 2
• Voltage - Supply: 3 V ~ 3.6 V
• Current - Supply: 50mA
• Power (watts): 150mW
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 144-LFQFP
• Includes: Bit Processor Functions, Serial Communication Controllers (SCCs)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: PEB20542FV1.3X; SP000007633

Table 16
Status Information
Length of received message
CRC result (good/bad)
Valid frame (yes/no)
ABORT sequence recognized (yes/no)
Data overflow (yes/no)
Results from address comparison
(with automatic address handling)
Type of frame (COMMAND/RESPONSE)
(with automatic address handling)
Type of Signaling Unit
(in SS7 mode)
ASYNC, BISYNC
• ’RPF’ (Receive Pool Full) interrupt, indicating that a specified number of bytes (refer
• ’TCD’ (Termination Character Detected) interrupt, indicating that reception has been
Additionally, the CPU can have access to contents of RFIFO without having received an
interrupt (and thereby causing ’TCD’ to occur) by issuing the RFIFO Read command
(CMDRH.RFRD).
In addition to every received character the assigned status information Parity bit (0/1),
Parity Error (yes/no), Framing Error (yes/no, ASYNC only!) is optionally stored in RFIFO.
With an end condition (’TCD’ interrupt or after ’RFRD’ command) the length of the last
received data block is stored in register RBCL. The number of bytes to read from RFIFO
is determined by the 1, 2, 4 or 5 least significant bits of register RBCL, depending on the
selected RFIFO threshold (bit field ’RFTH(1..0)’ in register CCR3H).
Note: (For all serial modes) After the received data has been read from the RFIFO, this
The data reception sequence, from the CPU’s point of view, is outlined in
Data Sheet
to register CCR3H, bit field ’RFTH(1..0)’) can be read from RFIFO.
terminated by reception of a specified character (refer to register
CCR3L.TCDE).
must be explicitly acknowledged by the CPU issuing an ’RMC’ (Receive Message
Complete) command. The CPU has to handle the ’RPF’ interrupt before the
complete 2 x 32-byte FIFO is filled up with receive data which would cause a
“Receive Data Overflow” condition.
Status Information after RME interupt
261
Location
registers RBCH,
RSTA
RSTA
RSTA
RSTA
RSTA
RSTA
RSTA
register (or last byte of received data)
register (or last byte of received data)
register (or last byte of received data)
register (or last byte of received data)
register (or last byte of received data)
register (or last byte of received data)
register (or last byte of received data)
RBCL
Programming
Figure
TCR
PEB 20542
PEF 20542
2000-09-14
and bit
60.