PEB2256H-V12 Infineon Technologies, PEB2256H-V12 Datasheet - Page 52

• Manufacturer Part Number: PEB2256H-V12
• Description: IC INTERFACE LINE 3.3V 80-MQFP
• Manufacturer: Infineon Technologies

Specifications of PEB2256H-V12

• Applications: *
• Interface: *
• Voltage - Supply: *
• Package / Case: 80-SQFP
• Mounting Type: Surface Mount
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: PEB2256H-V12; PEB2256H-V12IN

3.3
3.3.1
The communication between the CPU and the FALC56 is done using a set of directly
accessible registers. The interface can be configured as Intel or Motorola type with a
selectable data bus width of 8 or 16 bits.
The CPU transfers data to and from the FALC56 (through 64-byte deep FIFOs per
direction), sets the operating modes, controls function sequences, and gets status
information by writing or reading control and status registers. All accesses can be done
as byte or word accesses if enabled. If 16-bit bus width is selected, access to lower/
upper part of the data bus is determined by address line A0 and signal BHE/BLE as
shown in
Table 8
structure and interface type. The switching of ALE allows the FALC56 to be directly
connected to a multiplexed address/data bus.
3.3.1.1
Reading from or writing to the internal FIFOs (RFIFO and XFIFO) can be done using a
8-bit (byte) or 16-bit (word) access depending on the selected bus interface mode.
Randomly mixed byte/word access to the FIFOs is allowed without any restrictions.
Table 6
BHE
0
0
1
1
Table 7
BLE
0
0
1
1
Data Sheet
A0
0
1
0
1
shows how the ALE (Address Latch Enable) line is used to control the bus
A0
0
1
0
1
Table 6
Functional Blocks
Microprocessor Interface
Mixed Byte/Word Access to the FIFOs
Data Bus Access (16-Bit Intel Mode)
Data Bus Access (16-Bit Motorola Mode)
Register Access
FIFO word access
Register word access (even addresses)
Register byte access (odd addresses)
Register byte access (even addresses)
No transfer performed
Register Access
FIFO word access
Register word access (even addresses)
Register byte access (odd addresses)
Register byte access (even addresses)
No transfer performed
and
Table
7.
52
Functional Description E1/T1/J1
FALC56 Data Pins Used
D(15:0)
D(15:8)
D(7:0)
None
FALC56 Data Pins Used
D(15:0)
D(7:0)
D(15:8)
None
FALC56 V1.2
PEB 2256
2002-08-27