PEB2256H-V12 Infineon Technologies, PEB2256H-V12 Datasheet
PEB2256H-V12
Specifications of PEB2256H-V12
PEB2256H-V12IN
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PEB2256H-V12 Summary of contents
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... Infineon Technologies Office. Infineon Technologies Components may only be used in life-support devices or systems with the express written approval of Infineon Technologies failure of such components can reasonably be expected to cause the failure of that life-support device or system affect the safety or effectiveness of that device or system. Life support devices or systems are intended to be implanted in the human body support and/or maintain and sustain and/or protect human life ...
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Table of Contents 1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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Table of Contents 4.2.2 Doubleframe Format (E1 ...
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Table of Contents 4.6.1 Pseudo-Random Binary Sequence Generation and Monitor . . . . . . . . 114 4.6.2 Remote Loop . . . . . . . . . . . . . . . . . . ...
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Table of Contents 5.2.7.1 Synchronization Procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147 5.2.8 Summary ...
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Table of Contents 6.1 Operational Overview ...
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Table of Contents 11.4 AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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List of Figures Figure 1 Logic Symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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List of Figures Figure 43 Receive Line Monitoring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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List of Figures Figure 85 Intel Multiplexed Address Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . 453 Figure 86 ...
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List of Tables Table 1 Pin Definitions - Microprocessor Interface . . . . . . . . . . . . . . . . . . . . . . 29 Table 2 Pin Definitions - Line Interface ...
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List of Tables Table 43 Bit Functions in Periodical Performance Report . . . . . . . . . . . . . . . . 164 Table 44 System Clocking and Data Rates (T1/J1 ...
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List of Tables Table 85 FSC Timing Parameter Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 470 Table ...
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Preface The FALC56 framer and line interface component is designed to fulfill all required interfacing between an analog E1/T1/J1 line and the digital PCM system highway/H.100 bus. The digital functions as well as the analog characteristics are configured via a ...
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Organization of this Document This Data Sheet is organized as follows: • Chapter 1, Introduction Gives a general description of the product and its family, lists the key features, and presents some typical applications. • Chapter 2, Pin Descriptions Lists ...
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Related Documentation A detailed description of changes from version 1.1 to 1.2 is given in the "PEB 2256 Version 1.2 Delta Sheet". This document refers to the following international standards (in alphabetical/numerical order): ANSI/EIA-656 ANSI T1.102 ANSI T1.403 AT&T PUB ...
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Introduction The FALC56 framer and line interface component is designed to fulfill all required interfacing between analog E1/T1/J1 lines and the digital PCM system highway, H.100/H.110 or H-MVIP bus for world market telecommunication systems. Due to its multitude of ...
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E1/T1/J1 Framer and Line Interface Component for Long- and Short-Haul Applications FALC56 Version 1.2 1.1 Features Line Interface • High-density, generic interface for all E1/T1/J1 applications • Analog receive and transmit circuits for long-haul and short-haul applications • ...
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Support of automatic protection switching • Dual-rail or single-rail digital inputs and outputs • Unipolar NRZ or CMI for interfacing fiber-optical transmission routes • Selectable line codes (E1: HDB3, AMI/T1: B8ZS, AMI with ZCS) • Loss-of-signal indication with programmable ...
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Channel loop back, line loop back or payload loop back capabilities (TR54016) • Pseudo-random binary sequence generator and monitor (framed or unframed) • Clear channel capabilities (T1/J1) • Loop-timed mode Signaling Controller • Three HDLC controllers Bit stuffing, CRC ...
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General • Boundary scan standard IEEE 1149.1 • P-LBGA-81-1 package; body size 10 mm • P-MQFP-80-1 package; body size 14 mm • Temperature range from -40 to +85 °C • 3.3 V power supply, digital inputs 5V tolerant • Typical ...
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Logic Symbol Receive RL1/RDIP/ROID Line RL2/RDIN/RCLKI Interface TRS TDI Boundary TMS Scan TCK TDO Transmit XL1/XDOP/XOID Line XL2/XDON Interface V DDX V SSX Figure 1 Logic Symbol Data Sheet System Clocks SCLKR RDO RPA RPB RPC RPD FALC 56 ...
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Typical Applications The figures show a multiple link application for Frame Relay applications using the ® FALC 56 together with the 128-channel HDLC controller M128X and the Memory Timeswitch MTLS as well as an 8-channel interface to the ATM ...
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Port 1 FALC -56 R E1/T1/J1 PEB 2256 Port 8 FALC -56 R E1/T1/J1 PEB 2256 Figure 3 8-Channel E1/T1/J1-Interface to the ATM Layer Data Sheet RAM 8 x PCM UTOPIA IWE8 R PXB 4220 AAL1 or ATM-Mode 25 ...
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Pin Descriptions 2.1 Pin Diagram P-MQFP-80-1 (top view) 60 XPB 61 XPC XPD SCLKX 64 SCLKR RDO RPA RPB 68 RPC RPD MCLK N.C. RCLK CLK1 76 CLK2 SEC/FSC SYNC N. ...
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Pin Diagram P-LBGA-81 XPB B VSS BHE/ C BLE ALE VSS J VDD Figure 5 Pin Configuration P-LBGA-81-1 (bottom view) Data Sheet XPC SCLKR ...
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A VSSR RL2/ B RDIN XL2/ C XDON D VSSX TRS G TDI D15 Figure 6 Pin Configuration P-LBGA-81-1 (top view) Data Sheet SYNC RCLK NC VDD RPB ...
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Pin Definitions and Functions • Table 1 Pin Definitions - Microprocessor Interface Pin Ball Symbol No. No ...
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Table 1 Pin Definitions - Microprocessor Interface (cont’d) Pin Ball Symbol No. No ALE 52 E7 RD/ WR/ DBW Data Sheet Input (I) Function Output (O) Supply ( Address Latch Enable ...
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Table 1 Pin Definitions - Microprocessor Interface (cont’d) Pin Ball Symbol No. No BHE/ BLE 57 C7 INT Data Sheet Input (I) Function Output (O) Supply ( Interface Mode ...
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Table 2 Pin Definitions - Line Interface Pin Ball Symbol No. No RL1 RDIP ROID Data Sheet Input (I) Function Output (O) Supply (S) Line Interface Receive I (analog) Line Receiver 1 Analog input from the external ...
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Table 2 Pin Definitions - Line Interface (cont’d) Pin Ball Symbol No. No RL2 RDIN RCLKI Data Sheet Input (I) Function Output (O) Supply (S) I (analog) Line Receiver 2 Analog input from the external transformer. Selected if ...
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Table 2 Pin Definitions - Line Interface (cont’d) Pin Ball Symbol No. No XL1 XDOP XOID Data Sheet Input (I) Function Output (O) Supply (S) Line Interface Transmit O (analog) Transmit Line 1 Analog output to the external ...
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Table 2 Pin Definitions - Line Interface (cont’d) Pin Ball Symbol No. No XL2 XDON XFM Data Sheet Input (I) Function Output (O) Supply (S) O (analog) Transmit Line 2 Analog output for the external transformer. Selected if ...
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Table 3 Pin Definitions - Clock Generation Pin Pin Symbol No. No MCLK 79 A2 SYNC 76 B4 CLK1 Data Sheet Input (I) Function Output (O) Supply (S) Master Clock I A reference clock of better than ...
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Table 3 Pin Definitions - Clock Generation (cont’d) Pin Pin Symbol No. No CLK2 78 B3 SEC FSC Data Sheet Input (I) Function Output (O) Supply ( System Clock of DCO-X Output of the de-jittered ...
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Table 3 Pin Definitions - Clock Generation (cont’d) Pin Pin Symbol No. No RCLK Data Sheet Input (I) Function Output (O) Supply ( Receive Clock After reset this port is configured to be internally pulled ...
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Table 4 Pin Definitions - System Interface Pin Ball Symbol No. No RDO 65 A7 SCLKR Data Sheet Input (I) Function Output (O) Supply (S) System Interface Receive O Receive Data Out Received data that is sent ...
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Table 4 Pin Definitions - System Interface (cont’d) Pin Ball Symbol No. No RPA 68 A6 RPB 69 B5 RPC 70 D5 RPD Data Sheet Input (I) Function Output (O) Supply (S) I Receive Multifunction Port ...
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Table 4 Pin Definitions - System Interface (cont’d) Pin Ball Symbol No. No RPA 68 A6 RPB 69 B5 RPC 70 D5 RPD Data Sheet Input (I) Function Output (O) Supply (S) O Receive Frame Marker (RFM) PC(4:1).RPC(2:0) ...
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Table 4 Pin Definitions - System Interface (cont’d) Pin Ball Symbol No. No RPA 68 A6 RPB 69 B5 RPC 70 D5 RPD Data Sheet Input (I) Function Output (O) Supply (S) O Receive Signaling Marker (RSIGM) PC(1:4).RPC(2:0) ...
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Table 4 Pin Definitions - System Interface (cont’d) Pin Ball Symbol No. No RPA 68 A6 RPB 69 B5 RPC 70 D5 RPD 56 D8 XDI 64 C6 SCLKX Data Sheet Input (I) Function Output (O) Supply (S) ...
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Table 4 Pin Definitions - System Interface (cont’d) Pin Ball Symbol No. No XPA 61 A9 XPB 62 A8 XPC 63 B7 XPD Data Sheet Input (I) Function Output (O) Supply (S) I Transmit Multifunction Port ...
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Table 4 Pin Definitions - System Interface (cont’d) Pin Ball Symbol No. No XPA 61 A9 XPB 62 A8 XPC 63 B7 XPD Data Sheet Input (I) Function Output (O) Supply ( Synchronous Pulse Transmit ...
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Table 4 Pin Definitions - System Interface (cont’d) Pin Ball Symbol No. No XPA 61 A9 XPB 62 A8 XPC 63 B7 XPD Data Sheet Input (I) Function Output (O) Supply ( Transmit Clock (TCLK) ...
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Table 4 Pin Definitions - System Interface (cont’d) Pin Ball Symbol No. No XPA 61 A9 XPB 62 A8 XPC 63 B7 XPD Data Sheet Input (I) Function Output (O) Supply (S) O Data Link Bit Transmit (DLX) ...
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Table 5 Pin Definitions - Miscellaneous Pin Ball Symbol No. No DDR SSR DDX SSX ...
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Table 5 Pin Definitions - Miscellaneous (cont’d) Pin Ball Symbol No Boundary Scan/Joint Test Access Group (JTAG TRS 15 G1 TDI 16 F2 TMS 17 G3 TCK ...
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Functional Description E1/T1/J1 3.1 Functional Overview ® The FALC device contains analog and digital function blocks that are configured and controlled by an external microprocessor or microcontroller. The main interfaces are • Receive and transmit line interface • PCM ...
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Block Diagram • RL1/RDIP/ Long+Short ROID Haul Line RL2/RDIN/ Interface RCLKI Clock/Data Recovery XL1/XDOP/ Long + Short XOID Haul Transmit XL2/XDON/ Line Interface XFM Boundary Scan JTAG 1149 TDI TMS TCK TRS TDO Figure 7 Block Diagram Data Sheet ...
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Functional Blocks 3.3.1 Microprocessor Interface The communication between the CPU and the FALC56 is done using a set of directly accessible registers. The interface can be configured as Intel or Motorola type with a selectable data bus width of ...
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Table 8 Selectable Bus and Microprocessor Interface Configuration ALE IM Microprocessor interface Motorola Intel SS DD switching 0 Intel The assignment of registers with even/odd addresses to the data lines in case ...
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RFIFO Byte 32 4 Byte 4 3 Byte 3 2 Byte 2 1 Byte 1 D15 D8 Figure 8 FIFO Word Access (Intel Mode) RFIFO Byte 32 4 Byte 4 3 Byte 3 2 ...
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Interrupt Interface Special events in the FALC programmable characteristics (open drain or push-pull, defined by register IPC), which requests the CPU to read status information from the FALC ® the FALC . Since only one INT request output is ...
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After reading the assigned interrupt status registers ISR(5:0), the pointer in register GIS is cleared or updated if another interrupt requires service. If all pending interrupts are acknowledged by reading (GIS is reset), pin INT goes inactive. ...
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Boundary Scan Interface In the FALC56 a Test Access Port (TAP) controller is implemented. The essential part of the TAP is a finite state machine (16 states) controlling the different operational modes of the boundary scan. Both, TAP controller ...
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If no boundary scan operation is used, TRS has to be connected to RST or V TCK and TDI do not need to be connected since pullup transistors ensure high input levels in this case. Test handling (boundary scan operation) ...
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Master Clocking Unit The FALC56 provides a flexible clocking unit, which references to any clock in the range of 1. MHz supplied on pin MCLK. The clocking unit has to be tuned to the selected reference frequency ...
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Functional Description E1 4.1 Receive Path in E1 Mode RL1/RDIP/ROID Equalizer RL2/RDIN/RCLKI SYNC MCLK Figure 13 Receive Clock System (E1) 4.1.1 Receive Line Interface For data input, three different data types are supported: • Ternary coded signals received at ...
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Receive Equalization Network (E1) The FALC56 automatically recovers the signals received on pins RL1 range -43 dB. The maximum reachable length with a 22 AWG twisted pair cable is 1500 m. After reset the ...
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Table 10 RCLK Output Selection (E1) Clock Source Receive Data (2.048 Mbit/s on RL1/RL2, RDIP/ RDIN or ROID) Receive Data in case of LOS DCO-R The intrinsic jitter generated in the absence of any input jitter is not more than ...
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Line Figure 14 Receiver Configuration (E1) Table 11 Recommended Receiver Configuration Values (E1) 1) Parameter This includes all parasitic effects caused by circuit board design. 4.1.7 Receive Line ...
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E1/T1/J1 Receive Line resistive -20 dB network Figure 15 Receive Line Monitoring Table 12 External Component Recommendations (Monitoring) 1) Parameter ...
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E1/T1/J1 Transmit Line E1/T1/J1 Receive Line Figure 16 Protection Switching Application 4.1.8 Loss-of-Signal Detection (E1) There are different definitions for detecting Loss-Of-Signal (LOS) alarms in the ITU-T G.775 and ETS 300233. The FALC56 covers all these standards. The LOS indication ...
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LIM1.RIL(2:0) (see 8-bit register (PCD). The contents of the PCD register is multiplied by 16, which results in the number of pulse periods, i.e. the time which has to suspend until the alarm has to be detected. The programmable ...
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Slave mode In slave mode (LIM0.MAS = 0) the DCO-R is synchronized on the recovered route clock. In case of LOS the DCO-R switches automatically to Master mode. If bit CMR1.DCS is set automatic switching from RCLK to SYNC ...
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Figure 17 Jitter Attenuation Performance (E1) Also the requirements of ETSI TBR12/13 are satisfied. Insuring adequate margin against TBR12/13 output jitter limit with 15 UI input at 20 ...
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Jitter Tolerance (E1) The FALC56 receiver’s tolerance to input jitter complies with ITU for CEPT applications. Figure 18 shows the curves of different input jitter specifications stated below as well as the FALC56 performance. 1000 UI 100 10 1 ...
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Framer/Synchronizer (E1) The following functions are performed: • Synchronization on pulse frame and multiframe • Error indication when synchronization is lost. In this case, AIS is sent automatically to the system side and remote alarm is sent to the ...
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Frame alignment between system frame and receive route frame • Reporting and controlling of slips Controlled by special signals generated by the receiver, the unipolar bit stream is converted into bit-parallel data which is circularly written to the elastic ...
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slip condition is detected, a negative slip (one frame or one half of the current buffer size is skipped positive slip (one frame or one half of the current buffer size is read out twice) is performed at ...
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Receive Signaling Controller (E1) The signaling controller can be programmed to operate in various signaling modes. The FALC56 performs the following signaling and data link methods. 4.1.14.1 HDLC or LAPD access The FALC56 offers three independent HDLC channels. All ...
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In signaling controller transparent mode, fully transparent data reception without HDLC framing is performed, i.e. without flag recognition, CRC checking or bit stuffing. This allows user specific protocol variations. 4.1.14.2 Support of Signaling System #7 The HDLC controller of channel ...
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Idle Reset Counter values [CMDR2.RSUC = 1] in service SU in error Link failure [ISR1.SUEX = 1] ...
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S -Bit Access (E1) a The FALC56 supports the S • the access through register RSW • the access through registers RSA(8:4), capable of storing the information for a complete multiframe • the access through the 64 byte deep ...
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Because the CAS controller is working on the PCM highway side of the receive buffer, slips disturb the CAS data. SYPR SCLKR T TS31 TS0 RDO FAS/NFAS RSIG FAS/NFAS T = Time ...
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Additionally the FALC56 generates a receive signaling data change pointer (RSP1/2) which directly points to the updated RS(16:1) register. Because the CAS controller is working on the PCM highway side of the receive buffer, slips ...
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Framer Operating Modes (E1) 4.2.1 General Bit: FMR1.PMOD = 0 PCM line bit rate : Single frame length : Framing frequency : HDLC controller : Organization : The operating mode of the FALC56 is selected by programming the carrier ...
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Doubleframe Format (E1) The framing structure is defined by the contents of time slot 0 (refer to Table 16 Allocation of Bits Time Slot 0 (E1) Bit AlternateNumber Frames Frame Containing the Frame Alignment Signal ...
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Table 17 Transmit Transparent Mode (Doubleframe E1) Enabled by Framing – (int. gen.) XSP.TT0 via pin XDI TSWM.TSIF (int. gen.) TSWM.TSIS (int. gen.) TSWM.TRA (int. gen.) TSWM.TSA(8:4) (int. gen.) 1) pin XDI or XSIG or XFIFO buffer (signaling controller) 2) ...
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Reaching the synchronous state causes a frame alignment recovery interrupt status ISR2.FAR if enabled. Undisturbed operation starts with the beginning of the next doubleframe. 4.2.2.3 A-Bit Access If the FALC56 detects a remote alarm indication in the received data stream ...
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CRC-Multiframe (E1) The multiframe structure shown in the receiver and FMR1.XFS for the transmitter. Multiframe : Frame alignment : Multiframe alignment : CRC bits : CRC block size : CRC procedure : Table 18 CRC-Multiframe Structure (E1) Sub- Multiframe ...
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For transmit direction, contents of time slot 0 are additionally determined by the selected transparent mode. Table 19 Transmit Transparent Mode (CRC Multiframe E1) enabled by Framing + CRC – (int. gen.) XSP.TT0 via pin XDI TSWM.TSIF via pin XDI ...
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In doubleframe asynchronous state, counting of framing errors, CRC4 bit errors and detection of remote alarm is stopped. AIS is automatically sent to the backplane interface (can be disabled by bit FMR2.DAIS). Further on the updating of the registers RSW, ...
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A research for basic frame alignment is initiated if the CRC4 multiframe synchronization cannot be achieved within 8 ms and is started just after the ...
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S -Bit Access (E1) a Due to signaling procedures using the five S CRC multiframe structure, three possibilities of access by the microprocessor are implemented. • The standard procedure allows reading/writing the S further support. The S a • ...
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S 6-Bit Error Indication Counters a The S 6-bit error indication counter CRC2L/H (16 bits) counts the received S a sequence 0001 or 0011 in every CRC submultiframe. In the primary rate access digital section this counter option gives information ...
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Note: E-bits can be processed by the system interface. Setting bit TSWM.TSIS enables transparency for E-bits in transmit direction (refer to OUT of Primary BFA: Inhibit Incoming CRC-4 Performance Monitoring Reset all Timers Set FRS0.LFA/LMFA/NMF = 110 IN Primary BFA: ...
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Additional Receive Framer Functions (E1) 4.3.1 Error Performance Monitoring and Alarm Handling Alarm Indication Signal: Detection and recovery is flagged by bit FRS0.AIS and ISR2.AIS. Transmission is enabled by bit FMR1.XAIS. Loss-Of-Signal: Detection and recovery is flagged by bit ...
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Table 20 Summary of Alarm Detection and Release (E1) (cont’d) Alarm Detection Condition Remote Alarm in Y-bit = 1 received in CAS time slot 16 (TS16RA) multiframe alignment word Loss-of-Signal in all zeros for at least 16 time slot 16 ...
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CAS multiframe alignment or a receive slip occurs. The internal signaling buffer RS(16:1) is frozen. Optionally automatic freeze signaling is disabled by setting bit SIC3.DAF. 4.3.3 Error Counter The FALC56 offers six error counters where each of them ...
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The FALC56 also offers the ability to generate and detect a flexible in-band loop-up and loop-down pattern (LCR1.LLBP = 1). The loop-up and loop-down pattern is individually programmable from bits in length (LCR1.LAC1/0 and LCR1.LDC1/0). Programming of ...
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Transmit Path in E1 Mode 4.4.1 Transmitter (E1) The serial bit stream is processed by the transmitter which has the following functions: • Frame/multiframe synthesis of one of the two selectable framing formats • Insertion of service and data ...
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Transmit Line Interface (E1) The analog transmitter transforms the unipolar bit stream to ternary (alternate bipolar) return to zero signals of the appropriate programmable shape. The unipolar data is provided by the digital transmitter. Line Figure 23 Transmitter Configuration ...
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Transmit Jitter Attenuator (E1) The transmit jitter attenuator DCO-X circuitry generates a "jitter-free" transmit clock and meets the following requirements: ITU-T I.431, G. 703, G. 736 to 739, G.823 and ETSI TBR12/13. The DCO-X circuitry works internally with the ...
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XL1/ XDOP/ DR XOID DR XL2/ XDON XCLK TCLK (E1: 8MHz) (T1: 6MHz) Clocking MCLK Figure 24 Transmit Clock System (E1) Note Dual-Rail interface DCO-X Digital Controlled Oscillator transmit 4.4.4 Transmit Elastic Buffer (E1) The received bit stream ...
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Clock adaption between system clock (SCLKX) and internally generated transmit route clock (XCLK). • Compensation of input wander and jitter. • Frame alignment between system frame and transmit route frame • Reporting and controlling of slips Writing of received ...
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XL1/2 and if the transmit line current drops below the detection limit the high-impedance state is cleared. Two conditions are detected by the monitor: transmit line de-jitteredity (more than 31 consecutive zeros) indicated by FRS1.XLO and transmit line high current ...
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Support of Signaling System #7 The HDLC controller of channel 1 supports the signaling system #7 (SS7) which is described in ITU-Q.703. The following description assumes, that the reader is familiar with the SS7 protocol definition. SS7 support must ...
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Channel Associated Signaling CAS (E1, serial mode) In external signaling mode (serial mode) the signaling data received on port XSIG is sampled with the working clock of the transmit system interface (SCLKX) in combination with the transmit synchronization pulse ...
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System Interface in E1 Mode The FALC56 offers a flexible feature for system designers where for transmit and receive direction different system clocks and system pulses are necessary. The interface to the receive system highway is realized by two ...
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MHz cycle and is clocked off with the rising or falling edge of the clock which is in/ output on port SCLKR (see SIC3.RESR/X). Compared to the receive path the inverse functions are performed for the transmit direction. The ...
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Receive Signaling Buffer Receive Elastic Buffer Receive Data Receive Receive Jitter Clock Attenuator Transmit Signaling Buffer Transmit Elastic Buffer BYP Transmit Data Transmit Transmit Jitter Clock Attenuator Figure 27 System Interface (E1) Data Sheet RSIGM RSIG RMFB RFM Receive DLR ...
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Receive System Interface (E1) FRAME 1 FRAME 2 FRAME 3 RDO RMFB SYPR SYPR Trigger 1) Edge SCLKR 8.192 MHz SCLKR 2.048 MHz RDO/RSIG Bit 255 2 Mbit/s Data Rate RDO/RSIG 4 Mbit/s Data Rate (SCLKR = 8.192 MHz) ...
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Receive Offset Programming Depending on the selection of the synchronization signals (SYPR or RFM), different calculation formulas are used to define the position of the synchronization pulses. These formulas are given below, see of SYPR and RFM is always ...
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TS0 RDO SCLKR SIC3.RESR = 0 (falling edge) SCLKR SIC3.RESR = 1 (rising edge) SYPR SYPR SYPR Figure 29 SYPR Offset Programming (2.048 Mbit/s, 2.048 MHz) TS0 - CP0 ...
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TS0 RDO SCLKR SIC3.RESR = 0 (falling edge) SCLKR SIC3.RESR = 1 (rising edge) RFM RFM RFM BP = 251 Figure 31 RFM Offset Programming (2.048 ...
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Transmit System Interface (E1) XDI FRAME0 FRAME1 XMFB XMFS SYPX Trigger Edge SYPX T SCLKX XSIGM XDI/XSIG DLX Sa-Bit Marker XC0.SA8E-SA4E 1) only falling edge mode shown 2) delay T is programmable by XC0/1; Figure 33 Transmit System Interface ...
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XDI FRAME0 FRAME1 XMFB XMFS SYPX Trigger Edge SYPX SCLKX XSIGM Time-Slot Marker TTR1...4 SIC2.SICS2-0=000 XDI/XSIG 3) SIC2.SICS2-0=000 3) XDI/XSIG SIC2.SICS2-0=001 DLX Sa-Bit Marker XC0.SA8E-SA4E SIC2.SICS2-0=000 DLX Sa-Bit Marker XC0.SA8E-SA4E SIC2.SICS2-0=000 1) only falling edge mode shown 2) delay T ...
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Transmit Offset Programming The pulse length of SYPX is always the basic E1 bit width (488 ns), independent of the selected system highway clock and data frequency. SYPX Offset Calculation T: Time between beginning of SYPX pulse and beginning ...
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TS0 XDI SCLKX SIC3.RESX = 1 (rising edge) SCLKX SIC3.RESX = 0 (falling edge) SYPX SYPX SYPX Figure 35 SYPX Offset Programming (2.048 Mbit/s, 2.048 MHz) TS0 - CP0 ...
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Time Slot Assigner (E1) HDLC channel 1 offers the flexibility to connect data during certain time slots, as defined by registers RTR(4:1) and TTR(4:1), to the RFIFO and XFIFO, respectively. Any combinations of time slots can be programmed for ...
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Test Functions (E1) 4.6.1 Pseudo-Random Binary Sequence Generation and Monitor The FALC56 has the ability to generate and monitor 2 binary sequences (PRBS). The generated PRBS pattern is transmitted to the remote end on pins XL1/2 or XDOP/N and ...
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Payload Loop-Back To perform an effective circuit test a payload loop is implemented. The payload loop- back (FMR2.PLB) loops the data stream from the receiver section back to transmitter section. The looped data passes the complete receiver including the ...
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Local Loop The local loop-back mode selected by LIM0. disconnects the receive lines RL1/2 or RDIP/RDIN from the receiver. Instead of the signals coming from the line the data provided by the system interface is routed through ...
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Single Channel Loop-Back Each of the 32 time slots can be selected for loop-back from the system PCM input (XDI) to the system PCM output (RDO). This loop-back is programmed for one time slot at a time selected by ...
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Alarm Simulation (E1) Alarm simulation does not affect the normal operation of the device, i.e. all time slots remain available for transmission. However, possible reported to the processor or to the remote end when the device is in the ...
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Functional Description T1/J1 5.1 Receive Path in T1/J1 Mode RL1/RDIP/ROID Equalizer RL2/RDIN/RCLKI SYNC MCLK Figure 41 Receive Clock System (T1/J1) 5.1.1 Receive Line Interface (T1/J1) For data input, three different data types are supported: • Ternary coded signals received ...
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Receive Equalization Network (T1/J1) The FALC56 automatically recovers the signals received on pins RL1/2. The maximum reachable length with a 22 AWG twisted-pair cable is 2000 m (~6560 ft.). After reset the FALC56 is in short-haul mode, received signals ...
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Table 25 RCLK Output Selection (T1/J1) Clock Source Receive Data (1.544 Mbit/s on RL1/RL2, RDIP/RDIN or ROID) Receive Data in case of LOS DCO-R The intrinsic jitter generated in the absence of any input jitter is not more than 0.035 ...
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Line Figure 42 Receiver Configuration (T1/J1) Table 26 Recommended Receiver Configuration Values (T1/J1) 1) Parameter This includes all parasitic effects caused by circuit board design. Data Sheet t ...
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Receive Line Monitoring Mode For short-haul applications like shown in switched into receive line monitoring mode (LIM0.RLM = 1). One device is used as a short-haul receiver while the other is used as a short-haul monitor. In this mode ...
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In these kind of applications both devices are working in parallel for redundancy purpose (see one must be switched into transmit line tristate mode. If both channels are configured identically and supplied with the same system data ...
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Detection: An alarm is generated if the incoming data stream has no pulses (no transitions) for a certain number (N) of consecutive pulse periods. “No pulse” in the digital receive interface means a logical zero on pins RDIP/RDIN or ...
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This center function of DCO-R can be optionally disabled (CMR2.DCF = 1) in order to accept a gapped reference clock. In analog line interface mode the RCLK is always running. Only in digital line interface mode with single-rail data ...
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Table 28 System Clocking (T1/J1) (cont’d) Mode Internal LOS Active Slave yes Slave yes The jitter attenuator meets the jitter transfer requirements of the PUB 62411, PUB 43802, TR-TSY 009,TR-TSY 253, TR-TSY 499 and ITU-T I.431 and G.703 (refer to ...
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Jitter Tolerance (T1/J1) The FALC56 receiver’s tolerance to input jitter complies with ITU, AT&T and Telcordia requirements for T1 applications. Figure 46 shows the curves of different input jitter specifications stated below as well as the FALC56 performance. 1000 ...
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Output Jitter (T1/J1) According to the input jitter defined by PUB62411 the FALC56 generates the output jitter, which is specified in Table 29 Table 29 Output Jitter (T1/J1) Specification Lower Cutoff PUB 62411 kHz 10 Hz ...
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RBS1/0 = 00: two frame buffer or 386 bits Maximum of wander amplitude (peak-to-peak 648 ns) System interface clocking rate: modulo 2.048 MHz: 142 UI in channel translation mode channel translation mode ...
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The 24 received time slots (T1/J1) can be translated into the 32 system time slots (E1) in two different channel translation modes (FMR1.CTM). Unequipped time slots are set See Table 30. H Table 30 Channel Translation Modes ...
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Table 31 Receive Buffer Operation Modes (T1/J1) Buffer Size (SIC1.RBS1/0) 1) bypass short buffer 1 frame 2 frames 1) In bypass mode the clock provided on pin SCLKR is ignored. Clocking is done with RCLK. Figure 47 gives an idea ...
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S Figure 47 The Receive Elastic Buffer as Circularly Organized Memory Data Sheet Frame 2 Time Slots R’ R Slip Frame 1 Time Slots Moment of Slip Detection Write Pointer (Route ...
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Receive Signaling Controller (T1/J1) The signaling controller can be programmed to operate in various signaling modes. The FALC56 performs the following signaling and data link methods. 5.1.14.1 HDLC or LAPD access The FALC56 offers three independent HDLC channels. All ...
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CRC checking or bit stuffing. This allows user specific protocol variations. 5.1.14.2 Support of Signaling System #7 The HDLC controller of channel 1 supports the signaling system #7 (SS7) which is described in ...
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Idle Reset Counter values [CMDR2.RSUC = 1] in service SU in error Link failure [ISR1.SUEX = 1] ...
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CAS Bit-Robbing (T1/J1, serial mode) The signaling information is carried in the LSB of every sixth frame for each time slot. The signaling controller samples the bit stream either on the receive line side or if external signaling is ...
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BOM receiver have been switched on (MODE.HRAC/BRAC), an automatic switching between HDLC and BOM mode is enabled. If eight or more consecutive ones are detected, the BOM mode is entered. Upon detection of a flag in the data stream, the ...
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Framer Operating Modes (T1/J1) 5.2.1 General Activated with bit FMR1.PMOD = 1. PCM line bit rate : Single frame length : Framing frequency : Organization : Selection of one of the four permissible framing formats is performed by bits ...
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User controlled, exclusively, by the control bits described above in the non-auto mode (FMR4.AUTO = 0). 5.2.3 Addition for F12 and F72 Format FT and FS bit conditions, i.e. pulse frame alignment and multiframe alignment can be handled separately ...
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Auto-Mode Definite Candidate Multiple Candidates Depends on the Disturbance D One Disturbance : Figure 49 Influences on Synchronization Status (T1/J1) Data Sheet EXLS FRS DON DOFF Multiple Candidates EXLS, FRS FRS DON DOFF EXLS FRS 141 FALC56 ...
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Figure 49 gives an overview of influences on synchronization status for the case of different external actions. Activation of auto mode and non-auto mode is performed by bit FMR4.AUTO. Generally, for initiating resynchronization it is recommended to use bit: FMR0.EXLS ...
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Multiframe ( Format, T1/J1) Normally, this kind of multiframe structure only makes sense when using the CAS robbed-bit signaling. The multiframe alignment signal is located at the FS-bit position of every other frame (refer to Table ...
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Two errors within 4/5/6 multiframing bits lead to the asynchronous state only for the multiframing. Loss of multiframe alignment is reported by bit FRS0.LMFA. The state of terminal framing is not influenced. Now, the resynchronization ...
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Synchronization Procedures For multiframe synchronization the FAS-bits are observed. Synchronous state is reached if at least one framing candidate is definitely found, or the synchronizer is forced to lock onto the next available candidate (FMR0.FRS). In the synchronous state ...
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FALC56 stays in the asynchronous state, searching for a possible available framing pattern. This procedure is repeated until the framer has locked on the right pattern. This automatic synchronization mode has been added in order to reduce ...
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Remote alarm (yellow alarm) is indicated by setting bit 2 to zero in each time slot. An additional use of the D-bits for alarm indication is user defined and must be done externally. 5.2.7.1 Synchronization Procedure In the synchronous state ...
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Table 36 72-Frame Multiframe Structure (T1/J1) Frame Number – – – – – – – ...
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Summary of Frame Conditions (T1/J1) Table 37 Summary Frame Recover/Out of Frame Conditions (T1/J1) Format Frame Recover Condition F4 only one FT pattern found, optional forcing on next available FT framing candidate F12 (D4) FMR2.SSP = 0: Combined FT ...
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Additional Receive Framer Functions (T1/J1) 5.3.1 Error Performance Monitoring and Alarm Handling • Alarm Indication Signal: Detection and recovery is flagged by bit FRS0.AIS and ISR2.AIS. Transmission is enabled by bit FMR1.XAIS. • Loss-Of-Signal: Detection and recovery is flagged ...
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Table 38 Summary of Alarm Detection and Release (T1/J1) (cont’d) Alarm Detection Condition Yellow Alarm or RC1.RRAM = 0: Remote Alarm bit 255 consecutive time 1) (RRA) slots or FS-bit = 1 of frame12 in F12 ...
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Automatic clock source switching In slave mode (LIM0.MAS = 0) the DCO-R synchronizes on the recovered route clock. In case of loss-of-signal (LOS) the DCO-R switches to master mode automatically. If bit CMR1.DCS is set, automatic switching from RCLK ...
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Clear Channel Capability For support of common T1 applications, clear channels can be specified through the 3- byte register bank CCB(1:3). In this mode the contents of selected transmit time slots are not overwritten by internally or externally sourced ...
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are detected. Violations of these rules are indicated by setting the status bit FRS1.PDEN and the interrupt status bit ISR0.PDEN. Generation of the interrupt status is programmed ...
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Similar to the receive line interface three different data types are supported: Line Figure 50 Transmitter Configuration (T1/J1) Table 39 Recommended Transmitter Configuration Values (T1/J1) Parameter Characteristic Impedance [ ] ...
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It synchronizes either to the working clock of the transmit backplane interface or the clock provided on pin TCLK or the receive clock RCLK (remote loop/loop-timed). The DCO-X attenuates the incoming ...
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XL1/ XDOP/ DR XOID DR XL2/ XDON XCLK TCLK (E1: 8MHz) (T1: 6MHz) Clocking MCLK Figure 52 Transmit Clock System (T1/J1) Note Dual-Rail interface DCO-X Digital Controlled Oscillator transmit 5.4.4 Transmit Elastic Buffer (T1/J1) The transmit elastic store ...
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Maximum of wander channel translation mode 0 Maximum of wander channel translation mode 1 System interface clocking rate: modulo 1.544 MHz: Maximum of wander average delay after performing a slip: 96 bits ...
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XDI and XP(A:D) is programmable by bits SIC2.SICS(2:0), the remaining channel phases are cleared or ignored respectively. The following table gives an overview of the transmit buffer operating modes. Table 40 Transmit Buffer Operating ...
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Transmit Line Monitor (T1/J1) The transmit line monitor compares the transmit line current on XL1 and XL2 with an on- chip transmit line current limiter. The monitor detects faults on the primary side of the transformer indicated by a ...
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HDLC framing is performed. Optionally the FALC56 supports the continuous transmission of the XFIFO contents. Operating in HDLC or BOM mode “flags” or “idle” are transmitted as interframe timefill. The FALC56 offers the flexibility to insert data during certain time ...
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In external signaling mode the signaling data is sampled with the working clock of the transmit system interface (SCLKX) together with the transmit synchronous pulse (SYPX). Data on XSIG is latched in the bit positions per time ...
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Table 42 Structure of Periodical Performance Report (T1/J1) Octet No FLAG = 2 SAPI = 3 TEI = 4 CONTROL = 00000011 = unacklowledged frame ...
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Table 43 Bit Functions in Periodical Performance Report Bit Value Interpretation number of CRC error events = < number of CRC error events < number of CRC error ...
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System Interface in T1/J1 Mode The FALC56 offers a flexible feature for system designers where for transmit and receive direction different system clocks and system pulses are necessary. The interface to the receive system highway is realized by two ...
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MHz cycle and is clocked off with the rising or falling edge of the clock which is in/ output on port SCLKR (see SIC3.RESX/R). Receive Signaling Buffer Receive Elastic Buffer Receive Data Receive Receive Jitter Clock Attenuator Transmit Signaling ...
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Receive System Interface (T1/J1) RDO FRAME 1 FRAME 2 FRAME 3 RMFB SYPR SYPR Trigger 1) Edge SCLKR 8.192 MHz T SCLKR 1.544 MHz RDO/RSIG Bit 255 2 Mbit/s Data Rate RDO/RSIG 4 Mbit/s Data Rate Bit 0 (SCLKR ...
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Receive Offset Programming Depending on the selection of the synchronization signals (SYPR or RFM), different calculation formulas are used to define the position of the synchronization pulses. These formulas are given below, see of SYPR and RFM is always ...
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RDO SCLKR SIC3.RESR = 0 (falling edge) SCLKR SIC3.RESR = 1 (rising edge) SYPR SYPR SYPR Figure 56 SYPR Offset Programming (1.544 Mbit/s, 1.544 MHz) RDO (CP0) F ...
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RDO SCLKR SIC3.RESR = 0 (falling edge) SCLKR SIC3.RESR = 1 (rising edge) RFM RFM RFM BP = 188 (BP = bit position) Figure 58 ...
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SYPR SCLKR T TS31 TS0 RDO RSIG FS/DL- channel T = Time slot offset (RC0, RC1 FS/DL-bit ABCD = Signaling bits for time slots 1...24, time slot mapping according to ...
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SYPR SCLKR T TS23 TS0 RDO RSIG RSIG ...
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XDI FRAME1 FRAME2 XMFB XMFS SYPX Trigger Edge SYPX T SCLKX XSIGM Time Slot Marker XDI DLX DL Bit Marker 1) only falling edge mode shown 2) delay T is programmable by XC0/1; Figure 63 Transmit System Clocking: 1.544 MHz ...
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XDI FRAME1 FRAME2 XMFS SYPX Trigger Edge SYPX T SCLKX XSIGM Time-Slot Marker XTR1...4 SIC2.SICS2-0=000(001) XDI/XSIG SIC2.SICS2-0=000 XDI/XSIG SIC2.SICS2-0=001 DLX DL-Bit Marker SIC2.SICS2-0=000 DLX DL-Bit Marker SIC2.SICS2-0=001 1) only falling edge mode shown 2) delay T is programmable by XC0/1; ...
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SYPX SCLKX T TS31 TS0 XDI XSIG FS/DL- channel T = Time slot offset (RC0, RC1 FS/DL-bit ABCD = Signaling bits for time slots 1...24, time slot mapping according to ...
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Frame 1 RD0 XDI RMFB XMFB FS/ RD0 24 1 XDI DL 1) RSIGM XSIGM FS/ RD0 1 2 XDI DL 1) RSIGM XSIGM 1) RSIGM and XSIGM are programed via registers RTR1 channel 24 Figure 67 Signaling Marker for ...
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Frame 1 RD0 XDI RMFB XMFB FS/ RD0 24 1 XDI DL 1) RSIGM XSIGM FS/ RD0 1 2 XDI DL 1) RSIGM XSIGM 1) RSIGM and XSIGM will mark the robbed bit positions if XCO.BRM is set high Figure ...
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FS/DL data on system transmit highway (XDI), time slot 0: MSB 1 Figure 69 Transmit FS/DL Bits on XDI (T1/J1) 5.5.2.1 Transmit Offset Programming The pulse length of SYPR and RFM is always the basic T1/J1 bit width (648 ns) ...
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XDI SCLKX SIC3.RESX = 1 (rising edge) SCLKX SIC3.RESX = 0 (falling edge) SYPX SYPX SYPX Figure 70 SYPX Offset Programming (1.544 Mbit/s, 1.544 MHz) XDI (CP0) F ...
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Time Slot Assigner (T1/J1) HDLC channel 1 offers the flexibility to connect data during certain time slots, as defined by registers RTR(4:1) and TTR(4:1), to the RFIFO and XFIFO, respectively. Any combinations of time slots can be programmed for ...
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The format for receive FS/DL data transmission in time slot 0 of the system interface is as shown in Figure 63 below. In order to get an undisturbed reception even in the asynchronous state bit FMR2.DAIS has to be set. ...
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Test Functions (T1/J1) 5.6.1 Pseudo-Random Binary Sequence Generation and Monitor The FALC56 has the added ability to generate and monitor a 2 Random Binary Sequences (PRBS). The generated PRBS pattern is transmitted to the remote end on pins XL1/2 ...
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Payload Loop-Back To perform an effective circuit test a line loop is implemented. If the payload loop-back (FMR2.PLB) is activated the received 192 bits of payload data is looped back to the transmit direction. The framing bits, CRC6 and ...
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Local Loop The local loop-back mode, selected by LIM0. disconnects the receive lines RL1 RDIP/RDIN from the receiver. Instead of the signals coming from the line the data provided by system interface are routed through ...
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Single Channel Loop-Back (loop-back of time slots) The channel loop-back is selected by LOOP.ECLB = 1. Each of the 24 time slots can be selected for loop-back from the system PCM input (XDI) to the system PCM output (RDO). ...
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Alarm Simulation (T1/J1) Alarm simulation does not affect the normal operation of the device, i.e. all time slots remain available for transmission. However, possible real alarm conditions are not reported to the processor or to the remote end when ...
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J1-Feature Overview The Japanese J1 standard is very similar to the T1 standard, but differs in some details. To support these differences easily, the following features are provided within the FALC56: • CRC6 generation and checking according to ITU-JT ...
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Operational Description E1 6.1 Operational Overview E1 The FALC56 can be operated in two modes, which are either E1 mode or T1/J1 mode. The device is programmable via a microprocessor interface which enables byte or word access to all ...
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Table 46 Initial Values after Reset (E1) (cont’d) Register Reset Value Meaning LOOP 00 H XSW 00 H XSP 00 H TSWM 00 H XC0 00 H XC1 9C H RC0 00 H RC1 9C H IDLE 00 H ICB(4:1) ...
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Table 46 Initial Values after Reset (E1) (cont’d) Register Reset Value Meaning RAH(2: RAL(2: GCM(6:1) all Initialization For a correct start up of the primary access interface ...
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Table 47 Initialization Parameters (E1) (cont’d) Operational Set Up Select framing Framing additions Synchronization mode Signaling mode Features like channel loop-back, idle channel activation, extensions for signaling support, alarm simulation, etc. are activated later. Transmission of alarms (e.g. AIS, remote ...
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They are very helpful especially to meet requirements as specified in ETS300 011. Table 49 Framer Initialization (E1) XSP.AXS = 1 ETS300 011 C4.x for instance requires the sending of E-Bits in TS0 if ...
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Table 50 HDLC Controller Initialization (E1) (cont’d) IMR0.RME = 0 Unmask interrupts for HDLC processor requests. IMR0.RPF = 0 IMR1.XPR = 0 IMR4.RME2=0 IMR4.RPF2=0 IMR5.XPR2=0 IMR5.RME3=0 IMR5.RPF3=0 IMR5.XPR3=0 RTR3.TS16 = 1 Select TS16 for HDLC data reception and transmission. TTR3.TS16 ...
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Operational Description T1/J1 7.1 Operational Overview T1/J1 The FALC56 can be operated in two principle modes, which are either E1 mode or T1/ J1 mode. The device is programmable via a microprocessor interface which enables byte or word access ...
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Table 52 Initial Values after reset and FMR1.PMOD = 1 (T1/J1) (cont’d) Register Initiated Value SIC1 00 H SIC2 SIC3 00 H LOOP 00 H FMR4 00 H FMR5 00 H XC0 00 H XC1 9C H RC0 ...
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Table 52 Initial Values after reset and FMR1.PMOD = 1 (T1/J1) (cont’d) Register Initiated Value MODE 00 H MODE2 00 H MODE3 00 H RAH(2: RAL(2: GCM(6:1) all 00 H ...
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Table 53 Initialization Parameters (T1/J1) Basic Set Up Master clocking mode T1/J1 mode select Specification of line interface and clock generation Line interface coding Loss-of-signal detection/ recovery conditions System clocking and data rate Channel translation mode Transmit offset counters ...
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Specific T1/J1 Initialization The following is a suggestion for a basic initialization to meet most of the T1/J1 requirements. Depending on different applications and requirements any other initialization can be used. Table 54 Line Interface Initialization (T1/J1) Register Function FMR0.XC0/1 ...
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Table 55 Framer Initialization (T1/J1) Register FMR4.SSC1/0 Selection of framing sync conditions FMR4.FM1/0 Select framing format FMR2.AXRA = 1 The transmission of RAI via the line interface is done automatically by the FALC56 in case of Loss of Frame Alignment ...
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Table 56 HDLC Controller Initialization (T1/J1) MODE = 88 HDLC channel 1 receiver active, no address comparison. H MODE2= 88 HDLC channel 2 receiver active, no address comparison. H MODE3= 88 HDLC channel 2 receiver active, no address comparison. H ...