PEB2256H-V12 Infineon Technologies, PEB2256H-V12 Datasheet - Page 41

• Manufacturer Part Number: PEB2256H-V12
• Description: IC INTERFACE LINE 3.3V 80-MQFP
• Manufacturer: Infineon Technologies

Specifications of PEB2256H-V12

• Applications: *
• Interface: *
• Voltage - Supply: *
• Package / Case: 80-SQFP
• Mounting Type: Surface Mount
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: PEB2256H-V12; PEB2256H-V12IN

Table 4
Pin
No.
67
68
69
70
Data Sheet
Ball
No.
D6
A6
B5
D5
Pin Definitions - System Interface (cont’d)
Symbol
RPA
RPB
RPC
RPD
Input (I)
Output (O)
Supply (S)
O
O
Function
Receive Frame Marker (RFM)
PC(4:1).RPC(2:0) = 001
CMR2.IRSP = 0: The receive frame marker
can be active high for a 2.048-MHz (E1) or
1.544-MHz (T1/J1) period during any bit
position of the current frame. It is clocked off
with the rising or falling edge of SCLKR or
RCLK, depending on SIC3.RESR. Offset
programming is done by using registers
RC(1:0).
CMR2.IRSP = 1: Frame synchronization pulse
generated by the DCO-R circuitry internally.
Together with registers RC(1:0) the frame
begin on the receive system interface is
defined. This frame synchronization pulse is
active low for a 2.048-MHz (E1) or 1.544-MHz
(T1/J1) period.
Receive Multiframe Begin (RMFB)
PC(1:4).RPC(2:0) = 010
In E1 mode RMFB marks the beginning of
every received multiframe (RDO). Optionally
the time slot 16 CAS multiframe begin can be
marked (SIC3.CASMF). Active high for one
2.048-MHz period.
In T1/J1 mode the function depends on bit
XC0.MFBS:
MFBS = 1: RMFB marks the beginning of
every received multiframe (RDO).
MFBS = 0: RMFB marks the beginning of
every received superframe. Additional pulses
are provided every 12 frames when using ESF/
F24 or F72 format.
41
Pin Descriptions
FALC56 V1.2
PEB 2256
2002-08-27