PEB2256H-V12 Infineon Technologies, PEB2256H-V12 Datasheet - Page 237

• Manufacturer Part Number: PEB2256H-V12
• Description: IC INTERFACE LINE 3.3V 80-MQFP
• Manufacturer: Infineon Technologies

Specifications of PEB2256H-V12

• Applications: *
• Interface: *
• Voltage - Supply: *
• Package / Case: 80-SQFP
• Mounting Type: Surface Mount
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: PEB2256H-V12; PEB2256H-V12IN

XCO(10:8)
Transmit Control 1 (Read/Write)
Value after reset: 9C
XC1
XCO(7:0)
Data Sheet
XCO7
7
Transmit Offset
Initial value loaded into the transmit bit counter at the trigger edge of
SCLKX when the synchronous pulse on port SYPX/XMFS is active
Refer to register XC1.
A write access to this address resets the transmit elastic buffer to its
basic starting position. Therefore, updating the value should only be
done when the FALC56 is initialized or when the buffer should be
centered. As a consequence a transmit slip will occur.
Transmit Offset
Calculation of delay time T (SCLKX cycles) depends on the value X
of the “Transmit Offset” register XC(1:0):
0
5
with maximum delay = (256
with SC = system clock defined by SIC1.SSC(1:0)
with SD = 2.048 MHz
Delay time T = time between beginning of time slot 0 (bit 0, channel
phase 0) at XDI/XSIG and the initial edge of SCLKX after SYPX/
XMFS goes active.
See
H
T
T
page 111
direction together with these bits the TSWM.TSA(8:4) bits must
be set to enable transmission to the remote end transparently
through the FALC56.
4: X = 4 - T
maximum delay: X = 256
for further description.
237
SC/SD) -1
SC/SD - T + 4)
XCO0
FALC56 V1.2
E1 Registers
0
PEB 2256
2002-08-27
(23)