PEB2256H-V12 Infineon Technologies, PEB2256H-V12 Datasheet - Page 106

• Manufacturer Part Number: PEB2256H-V12
• Description: IC INTERFACE LINE 3.3V 80-MQFP
• Manufacturer: Infineon Technologies

Specifications of PEB2256H-V12

• Applications: *
• Interface: *
• Voltage - Supply: *
• Package / Case: 80-SQFP
• Mounting Type: Surface Mount
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: PEB2256H-V12; PEB2256H-V12IN

4.5.1.1
Depending on the selection of the synchronization signals (SYPR or RFM), different
calculation formulas are used to define the position of the synchronization pulses. These
formulas are given below, see
of SYPR and RFM is always the basic E1 bit width (488 ns), independent of the selected
system highway clock and data frequency.
SYPR Offset Calculation
T:
SD:
SC:
X:
0
5
RFM Offset Calculation
MP:
SD:
SC:
X:
0
2046
Data Sheet
T
T
4:
T
MP
MP
Time between beginning of SYPR pulse and beginning of next frame
(time slot 0, bit 0), measured in number of SCLKR clock intervals
maximum delay: T
Basic data rate; 2.048 Mbit/s
System clock rate; 2.048, 4.096, 8.192, or 16.384 MHz
Programming value to be written to registers RC0 and RC1 (see
Marker position of RFM, counting in SCLKR clock cycles
(0 = bit 1, time slot 0, channel phase 0)
SC = 2.048 MHz:
SC = 4.096 MHz:
SC = 8.192 MHz:
SC = 16.384 MHz: 0
Basic data rate; 2.048 Mbit/s
System clock rate; 2.048, 4.096, 8.192, or 16.384 MHz
Programming value to be written to registers RC0 and RC1 (see
max
Receive Offset Programming
: X = 2052 - T
2045:
2047:
X = 4 - T
X = MP + 2
X = MP - 2046
max
0
0
0
Figure 29
= (256
MP
MP
MP
MP
255
511
1023
2047
SC/SD) - 1
to
106
Figure 32
for explanation. The pulse length
Functional Description E1
FALC56 V1.2
page
page
PEB 2256
2002-08-27
239).
239).