PEB2256H-V12 Infineon Technologies, PEB2256H-V12 Datasheet - Page 229

• Manufacturer Part Number: PEB2256H-V12
• Description: IC INTERFACE LINE 3.3V 80-MQFP
• Manufacturer: Infineon Technologies

Specifications of PEB2256H-V12

• Applications: *
• Interface: *
• Voltage - Supply: *
• Package / Case: 80-SQFP
• Mounting Type: Surface Mount
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: PEB2256H-V12; PEB2256H-V12IN

FRS
SIM
Data Sheet
0 =
1 =
Force Resynchronization
A transition from low to high initiates a resynchronization procedure
of the pulse frame and the CRC-multiframe (if enabled by bit
FMR2.RFS1) starting directly after the old framing candidate.
Alarm Simulation
0 =
1 =
SIM has to be held stable at high or low level for at least one receive
clock period before changing it again.
The AIS alarm is detected according to ETS300233.
Detection: An AIS alarm is detected if the incoming data stream
contains less than 3 zeros within a period of 512 bits and a loss
of frame alignment is indicated.
Recovery: The alarm is cleared if 3 or more zeros within 512
bits are detected or the FAS word is found.
The AIS alarm is detected according to ITU-T G.775
Detection: An AIS alarm is detected if the incoming data stream
contains less than 3 zeros in each doubleframe period of two
consecutive doubleframe periods (1024 bits).
Recovery: The alarm is cleared if 3 or more zeros are detected
within two consecutive doubleframe periods.
Normal operation.
Initiates internal error simulation of AIS, loss-of-signal, loss of
synchronization, remote alarm, slip, framing errors, CRC
errors, and code violations. The error counters FEC, CVC,
CEC1 are incremented.
229
FALC56 V1.2
E1 Registers
PEB 2256
2002-08-27