PEB2256H-V12 Infineon Technologies, PEB2256H-V12 Datasheet - Page 222

• Manufacturer Part Number: PEB2256H-V12
• Description: IC INTERFACE LINE 3.3V 80-MQFP
• Manufacturer: Infineon Technologies

Specifications of PEB2256H-V12

• Applications: *
• Interface: *
• Voltage - Supply: *
• Package / Case: 80-SQFP
• Mounting Type: Surface Mount
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: PEB2256H-V12; PEB2256H-V12IN

EITS
ITF
XMFA
Data Sheet
Determines the synchronization mode of the channel associated
signaling multiframe alignment.
0 =
1 =
Enable Internal Time Slot 0 to 31 Signaling
0 =
1 =
Interframe Time Fill
Determines the idle (= no data to be sent) state of the transmit data
coming from the signaling controller.
0 =
1 =
Transmit Multiframe Aligned
Determines the synchronization between the framer and the
corresponding signaling controller.
0 =
1 =
Note: During the transmission of the XFIFO content, the SYPX or
XMFS interval time should not be changed, otherwise the
XFIFO data has to be retransmitted.
Synchronization is done in accordance to ITU-T G. 732
Synchronization is established when two consecutively correct
multiframe alignment pattern are found.
Internal signaling in time slots 0 to 31 defined by registers
RTR(4:1) or TTR(4:1) is disabled.
Internal signaling in time slots 0 to 31 defined by registers
RTR(4:1) or TTR(4:1) is enabled.
Continuous logical "1" is output
Continuous flag sequences are output ("01111110" bit
patterns)
The contents of the XFIFO is transmitted without multiframe
alignment.
The contents of the XFIFO is transmitted multiframe aligned.
The first byte in XFIFO is transmitted in the first time slot
selected by TTR(4:1) and so on.
After reception of a complete multiframe in the time slot mode
(RTR(4:1)) an ISR0.RME interrupt is generated, if no HDLC
mode is enabled
In S
a
-bit access mode XMFA is not valid.
222
FALC56 V1.2
E1 Registers
PEB 2256
2002-08-27