PEB2256H-V12 Infineon Technologies, PEB2256H-V12 Datasheet - Page 101

• Manufacturer Part Number: PEB2256H-V12
• Description: IC INTERFACE LINE 3.3V 80-MQFP
• Manufacturer: Infineon Technologies

Specifications of PEB2256H-V12

• Applications: *
• Interface: *
• Voltage - Supply: *
• Package / Case: 80-SQFP
• Mounting Type: Surface Mount
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: PEB2256H-V12; PEB2256H-V12IN

4.4.7.4
In external signaling mode (serial mode) the signaling data received on port XSIG is
sampled with the working clock of the transmit system interface (SCLKX) in combination
with the transmit synchronization pulse (SYPX). Data on XSIG is latched in the bit
positions 5 to 8 per time slot, bits 1 to 4 are ignored. Time slots 0 and 16 are sampled
completely (bit 1 to 8). The received CAS multiframe is inserted frame aligned into the
data stream on XDI and must be valid during the last frame of a multiframe if CRC4/
multiframe mode is selected. The CAS multiframe is aligned to the CRC4-multiframe;
other frames are ignored. Data sourced by the internal signaling controller (µP access
mode) overwrites the external signaling data.
If the FALC56 is configured for no signaling, the system interface data stream passes
the FALC56 undisturbedly.
Note: CAS data on XSIG is read in the last frame of a multiframe only and ignored in all
Figure 26
4.4.7.5
Transmit data stored in registers XS(16:1) is transmitted on a multiframe boundary in
time slot 16. The signaling controller inserts the bit stream either on the transmit line side
or, if external signaling is enabled, on the transmit system side using pin function XSIG.
Data sourced by the internal signaling controller overwrites the external signaling data.
If the FALC56 is configured for no signaling, the system interface data stream passes
the FALC56 undisturbedly.
Data Sheet
SYPX
SCLKX
XDI
XSIG
other frames.
Channel Associated Signaling CAS (E1, serial mode)
Channel Associated Signaling CAS (E1, µP access mode)
T
FAS
NFAS
ABCD
0000XYXX
A B C D
4 5 6 7
2.048 MHz Transmit Signaling Highway (E1)
TS31
T
FAS/NFAS
FAS/NFAS
= Time slot offset (XC0, XC1)
= Frame alignment signal, is taken from XSIG, not from XDI
= TS0 not containing FAS
= Signaling bits for time slots 1...15 and 17...31 of CAS multiframe
= CAS multiframe alignment signal, has to be provided in TS16
TS0
0 1 2 3 4 5 6 7
TS1
A B C D
125 µs
101
0 1 2 3 4 5 6 7
0 0 0 0 X Y X X
TS16
Functional Description E1
0 1 2 3 4 5 6 7
FALC56 V1.2
TS31
A B C D
PEB 2256
2002-08-27
F0132