PEB2256H-V12 Infineon Technologies, PEB2256H-V12 Datasheet - Page 240

• Manufacturer Part Number: PEB2256H-V12
• Description: IC INTERFACE LINE 3.3V 80-MQFP
• Manufacturer: Infineon Technologies

Specifications of PEB2256H-V12

• Applications: *
• Interface: *
• Voltage - Supply: *
• Package / Case: 80-SQFP
• Mounting Type: Surface Mount
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: PEB2256H-V12; PEB2256H-V12IN

FALC56 V1.2
PEB 2256
E1 Registers
Delay time T = time between beginning of time slot 0 at RDO and the
initial edge of SCLKR after SYPR goes active.
See
page 106
for further description.
Receive Frame Marker Offset (PC(4:1).RPC(2:0) = 001
)
B
Offset programming of the receive frame marker which is output on
multifunction port RFM. The receive frame marker can be activated
during any bit position of the entire frame and depends on the
selected system clock rate.
Calculation of the value X of the receive offset register RC(1:0)
depends on the bit position which should be marked at marker
position MP:
0
MP
2045:X = MP + 2
2046
MP
2047: X = MP - 2046
e.g: 2.048 MHz: MP = 0 to 255; up to 16.384 MHz: MP = 0 to 2047
Data Sheet
240
2002-08-27