PEB2256H-V12 Infineon Technologies, PEB2256H-V12 Datasheet - Page 351

• Manufacturer Part Number: PEB2256H-V12
• Description: IC INTERFACE LINE 3.3V 80-MQFP
• Manufacturer: Infineon Technologies

Specifications of PEB2256H-V12

• Applications: *
• Interface: *
• Voltage - Supply: *
• Package / Case: 80-SQFP
• Mounting Type: Surface Mount
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: PEB2256H-V12; PEB2256H-V12IN

EXZE
LOOP (Read/Write)
Value after reset: 00
LOOP
RTM
ECLB
CLA(4:0)
Data Sheet
7
Excessive Zeros Detection Enable
Selects error detection mode in the bipolar receive bit stream.
0 =
1 =
Receive Transparent Mode
Setting this bit disconnects control of the internal elastic store from the
receiver. The elastic store is now in a “free running” mode without any
possibility to actualize the time slot assignment to a new frame
position in case of resynchronization of the receiver. This function can
be used together with the “disable AIS to system interface” feature
(FMR2.DAIS) to realize undisturbed transparent reception.
This bit should be enabled in case of unframed data reception mode.
Enable Channel Loop-Back
0 =
1 =
Note: CAS-BR must be switched off (FMR5.EIBR = 0) while channel
Channel Address For Loop-Back
CLA = 1 to 24 selects the channel.
During loop-back, the contents of the associated outgoing channel on
ports XL1/XDOP/XOID and XL2/XDON is equal to the idle channel
code programmed in register IDLE.
RTM
H
Disables the channel loop-back.
Enables the channel loop-back selected by this register.
Only bipolar violations are detected.
Bipolar violations and zero strings of 8 or more contiguous
zeros in B8ZS code or more than 15 contiguous zeros in AMI
code are detected additionally and counted in the code
violation counter CVC.
loop back is enabled.
ECLB
CLA4
351
CLA3
CLA2
CLA1
T1/J1 Registers
CLA0
FALC56 V1.2
0
PEB 2256
2002-08-27
(1F)