PEB2256H-V12 Infineon Technologies, PEB2256H-V12 Datasheet - Page 32

• Manufacturer Part Number: PEB2256H-V12
• Description: IC INTERFACE LINE 3.3V 80-MQFP
• Manufacturer: Infineon Technologies

Specifications of PEB2256H-V12

• Applications: *
• Interface: *
• Voltage - Supply: *
• Package / Case: 80-SQFP
• Mounting Type: Surface Mount
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: PEB2256H-V12; PEB2256H-V12IN

•
Table 2
Pin
No.
3
Data Sheet
Ball
No.
C2
Pin Definitions - Line Interface
Symbol
RL1
RDIP
ROID
Input (I)
Output (O)
Supply (S)
I (analog)
I
I
Line Interface Receive
Function
Line Receiver 1
Analog input from the external transformer.
Selected if LIM1.DRS is cleared.
Receive Data Input Positive
Digital input for received dual-rail PCM(+) route
signal which is latched with the internally
recovered receive route clock. An internal
DPLL extracts the receive route clock from the
incoming data pulses. The duty cycle of the
received signal has to be close to 50%.
The dual-rail mode is selected if LIM1.DRS
and FMR0.RC1 are set. Input polarity is
selected by bit RC0.RDIS (after reset: active
low), line coding is selected by FMR0.RC(1:0).
Receive Optical Interface Data
Unipolar data received from a fiber-optical
interface with 2048 kbit/s (E1) or 1544 kbit/s
(T1/J1). Latching of data is done with the falling
edge of RCLKI. Input polarity is selected by bit
RC0.RDIS.
The single-rail mode is selected if LIM1.DRS is
set and FMR0.RC1 is cleared.
If CMI coding is selected
(FMR0.RC(1:0) = 01), an internal DPLL
recovers clock an data; no clock signal on
RCLKI is required.
32
Pin Descriptions
FALC56 V1.2
PEB 2256
2002-08-27