PEB2256H-V12 Infineon Technologies, PEB2256H-V12 Datasheet - Page 421

• Manufacturer Part Number: PEB2256H-V12
• Description: IC INTERFACE LINE 3.3V 80-MQFP
• Manufacturer: Infineon Technologies

Specifications of PEB2256H-V12

• Applications: *
• Interface: *
• Voltage - Supply: *
• Package / Case: 80-SQFP
• Mounting Type: Surface Mount
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: PEB2256H-V12; PEB2256H-V12IN

COFA Event Counter (Read)
COEC
COE(7:2)
COE(1:0)
Data Sheet
COE7
7
Multiframe Counter
If GCR.ECMC = 1 this 6 bit counter increments with each multiframe
period in the asynchronous state FRS0.LFA/LMFA = 1. The error
counter does not roll over.
Change of Frame Alignment Counter
If GCR.ECMC = 1 this 2 bit counter increments with each detected
change of frame/multiframe alignment. The error counter does not roll
over.
During alarm simulation, the counter is incremented once per
multiframe.
Clearing and updating the counter is done according to bit
FMR1.ECM.
If this bit is reset the error counter is permanently updated in the
buffer. For correct read access of the event counter bit DEC.DCOEC
has to be set. With the rising edge of this bit updating the buffer is
stopped and the error counter is reset. Bit DEC.DCOEC is
automatically reset with reading the error counter high byte on
address 5B
If FMR1.ECM is set every second (interrupt ISR3.SEC) the error
counter is latched and then automatically reset. The latched error
counter state should be read within the next second.
H
. Data read on 5B
421
H
is not defined.
COE2
COE1
T1/J1 Registers
COE0
FALC56 V1.2
0
PEB 2256
2002-08-27
(5A)