ISP1161A1BM ST-Ericsson Inc, ISP1161A1BM Datasheet - Page 99

• Manufacturer Part Number: ISP1161A1BM
• Description: IC USB HOST/DEVICE CTRLR 64-LQFP
• Manufacturer: ST-Ericsson Inc

Specifications of ISP1161A1BM

• Controller Type: USB 2.0 Controller
• Interface: Parallel
• Voltage - Supply: 3.3V, 5V
• Current - Supply: 47mA
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 64-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 568-1163; ISP1161A1BM,557

Philips Semiconductors
Table 86:
[1]
9397 750 13961
Product data
Bit
Symbol
Reset
Access
Bit
Symbol
Reset
Access
Unchanged by a bus reset.
DcDMAConfiguration register: bit allocation
CNTREN
R/W
R/W
0
0
15
7
[1]
[1]
13.1.7 DcDMACounter register (R/W: F3H/F2H)
SHORTP
Table 87:
For selecting an endpoint for device DMA transfer, see
This command accesses the DcDMACounter register. The bit allocation is given in
Table
the register returns the number of remaining bytes in the current transfer. A bus reset
will not change the programmed bit values.
Bit
15
14
13 to 9
8
7 to 4
3
2
1 to 0
R/W
R/W
0
0
14
6
[1]
[1]
EPDIX[3:0]
88. Writing to the register sets the number of bytes for a DMA transfer. Reading
DcDMAConfiguration register: bit description
Symbol
CNTREN
SHORTP
-
ODD_EVEN_
IND
EPDIX[3:0]
DMAEN
-
BURSTL[1:0]
reserved
R/W
R/W
0
0
13
5
[1]
[1]
Rev. 03 — 23 December 2004
reserved
Description
A logic 1 enables the generation of an EOT condition, when the
DMA Counter register reaches zero. Bus reset value:
unchanged.
A logic 1 enables short/empty packet mode. When receiving
(OUT endpoint) a short/empty packet an EOT condition is
generated. When transmitting (IN endpoint), this bit should be
cleared. Bus reset value: unchanged.
reserved
This bit is logic 0 when the last DMA access is a byte (LSB byte
valid; MSB byte invalid). This bit is logic 1 when the last DMA
access is a word (LSB byte valid; MSB byte invalid).
Indicates the destination endpoint for DMA, see
Writing a logic 1 enables DMA transfer, a logic 0 forces the end
of an ongoing DMA transfer. Reading this bit indicates whether
DMA is enabled (0 = DMA stopped, 1 = DMA enabled). This bit
is cleared by a bus reset.
reserved
Selects the DMA burst length:
00 — single-cycle mode (1 byte)
01 — burst mode (4 bytes)
10 — burst mode (8 bytes)
11 — burst mode (16 bytes).
Bus reset value: unchanged.
R/W
R/W
0
0
12
4
[1]
[1]
reserved
DMAEN
USB single-chip host and device controller
R/W
R/W
0
11
3
0
[1]
reserved
reserved
R/W
R/W
0
10
2
0
[1]
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
Section
ISP1161A1
reserved
11.2.
R/W
R/W
0
0
9
1
[1]
[1]
BURSTL[1:0]
Table
EVEN_IND
70.
ODD_
R/W
98 of 136
0
R
8
0
0
[1]