ISP1161A1BM ST-Ericsson Inc, ISP1161A1BM Datasheet - Page 39

• Manufacturer Part Number: ISP1161A1BM
• Description: IC USB HOST/DEVICE CTRLR 64-LQFP
• Manufacturer: ST-Ericsson Inc

Specifications of ISP1161A1BM

• Controller Type: USB 2.0 Controller
• Interface: Parallel
• Voltage - Supply: 3.3V, 5V
• Current - Supply: 47mA
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 64-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 568-1163; ISP1161A1BM,557

Philips Semiconductors
9397 750 13961
Product data
Fig 32. HC time domain behavior: example 3.
(frame N)
9.5.2 Control transaction limitations
9.6 Microprocessor loading
9.7 Internal pull-down resistors for downstream ports
The different phases of a Control transfer (SETUP, Data and Status) should never be
put in the same ATL.
The maximum amount of data that can be transferred for an endpoint in one frame is
1023 bytes. The number of USB packets that are needed for this batch of data
depends on the maximum packet size that is specified.
The HCD has to schedule the transactions in a frame. On the other hand, the
microprocessor must have the ability to handle the interrupts coming from the HC
every 1 ms. It must also be able to do the scheduling for the next frame, reading the
frame information from and writing the next frame information to the buffer RAM in the
time between the end of the current frame and the start of the next frame.
There are four internal 15 k pull-down resistors built into the ISP1161A1 for the two
downstream ports: two resistors for each port. These resistors are software
selectable by programming bit 12 (2_DownstreamPort15KresistorSel) of the
HcHardwareConfiguration register (20H to read, A0H to write). When bit 12 is logic 0,
external 15 k pull-down resistors are used. When bit 12 is logic 1, internal 15 k
pull-down resistors are used. See
This feature is a cost-saving option. However, the power-on reset default value of
bit 12 is logic 0. If using the internal resistors, the HCD must set this bit status after
every reset, because a reset action (hardware or software) will clear this bit.
(frame N 1)
Rev. 03 — 23 December 2004
Figure
(frame N 2)
USB single-chip host and device controller
33.
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
(frame N 3)
ISP1161A1
MGT956
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