ISP1161A1BM ST-Ericsson Inc, ISP1161A1BM Datasheet - Page 17

• Manufacturer Part Number: ISP1161A1BM
• Description: IC USB HOST/DEVICE CTRLR 64-LQFP
• Manufacturer: ST-Ericsson Inc

Specifications of ISP1161A1BM

• Controller Type: USB 2.0 Controller
• Interface: Parallel
• Voltage - Supply: 3.3V, 5V
• Current - Supply: 47mA
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 64-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 568-1163; ISP1161A1BM,557

Philips Semiconductors
9397 750 13961
Product data
Fig 16. Internal FIFO buffer RAM access cycle.
write command
(16 bits)
8.4 FIFO buffer RAM access by PIO mode
Since the ISP1161A1 internal memory is structured as a FIFO buffer RAM, the FIFO
buffer RAM is mapped to dedicated register fields. Therefore, accessing the internal
FIFO buffer RAM is similar to accessing the internal control registers in multiple data
phases.
Figure 16
write cycle, the microprocessor first writes the FIFO buffer RAM’s command code to
the command port, and then writes the data words one by one to the data port until
half of the transfer’s byte count is reached. The HcTransferCounter register (22H to
read, A2H to write) is used to specify the byte count of a FIFO buffer RAM’s read
cycle or write cycle. Every access cycle must be in the same access direction. The
read cycle procedure is similar to the write cycle.
For access to the DC FIFO buffer RAM, see
Fig 15. Accessing DC control registers.
WR
RD
CS
D [ 15:0 ]
A1, A0
shows a complete access cycle of the HC internal FIFO buffer RAM. For a
FIFO buffer RAM access cycle (transfer counter = 2N)
read/write data
#1 (16 bits)
Rev. 03 — 23 December 2004
DC command
write
code
11
read/write data
#2 (16 bits)
USB single-chip host and device controller
DC register data
(lower word)
write
write
read
read
10
Section
13.
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
read/write data
#N (16 bits)
DC register data
(upper word)
ISP1161A1
write
write
read
read
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