ISP1161A1BM ST-Ericsson Inc, ISP1161A1BM Datasheet - Page 14

• Manufacturer Part Number: ISP1161A1BM
• Description: IC USB HOST/DEVICE CTRLR 64-LQFP
• Manufacturer: ST-Ericsson Inc

Specifications of ISP1161A1BM

• Controller Type: USB 2.0 Controller
• Interface: Parallel
• Voltage - Supply: 3.3V, 5V
• Current - Supply: 47mA
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 64-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 568-1163; ISP1161A1BM,557

Philips Semiconductors
9397 750 13961
Product data
8.3.1 I/O port addressing
8.3 Control register access by PIO mode
Figure 9
ISP1161A1. The ISP1161A1 provides two DMA channels:
The EOT signal is an external end-of-transfer signal used to terminate the DMA
transfer. Some microprocessors may not have this signal. In this case, the
ISP1161A1 provides an internal EOT signal to terminate the DMA transfer as well.
Setting the HcDMAConfiguration register (21H to read, A1H to write) enables the
ISP1161A1 HC internal DMA counter for DMA transfer. When the DMA counter
reaches the value set in the HcTransferCounter register (22H to read, A2H to write),
an internal EOT signal will be generated to terminate the DMA transfer.
Table 3
address should include the chip select signal CS and the address lines A1 and A0.
However, the direction of the access of the I/O ports is controlled by the RD and WR
signals. When RD is LOW, the microprocessor reads data from the ISP1161A1 data
port. When WR is LOW, the microprocessor writes a command to the command port,
or writes data to the data port.
Table 3:
Port
0
1
2
3
•
•
Fig 9. DMA interface between a microprocessor and an ISP1161A1.
DMA channel 1 (controlled by DREQ1, DACK1 signals) is for the DMA transfer
between a microprocessor’s system memory and the ISP1161A1 HC internal
FIFO buffer RAM.
DMA channel 2 (controlled by DREQ2, DACK2 signals) is for the DMA transfer
between a microprocessor system memory and the ISP1161A1 DC internal FIFO
buffer RAM.
shows the ISP1161A1 I/O port addressing. Complete decoding of the I/O port
shows the DMA interface between a microprocessor system and the
CS
0
0
0
0
I/O port addressing
Rev. 03 — 23 December 2004
PROCESSOR
A1,A0
(Bin)
00
01
10
11
MICRO-
DREQ1
DREQ2
DACK1
DACK2
D [ 15:0 ]
Access
R/W
W
R/W
W
EOT
WR
RD
USB single-chip host and device controller
P bus I/F
Data bus width
(bits)
16
16
16
16
D [ 15:0 ]
RD
WR
DACK1
DREQ1
DACK2
DREQ2
EOT
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
ISP1161A1
ISP1161A1
004aaa179
Description
HC data port
HC command port
DC data port
DC command port
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