ISP1161A1BM ST-Ericsson Inc, ISP1161A1BM Datasheet - Page 87

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ISP1161A1BM

Manufacturer Part Number
ISP1161A1BM
Description
IC USB HOST/DEVICE CTRLR 64-LQFP
Manufacturer
ST-Ericsson Inc
Datasheet

Specifications of ISP1161A1BM

Controller Type
USB 2.0 Controller
Interface
Parallel
Voltage - Supply
3.3V, 5V
Current - Supply
47mA
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
64-LQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
568-1163
ISP1161A1BM,557

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Philips Semiconductors
9397 750 13961
Product data
12.2 8237 compatible mode
Table 70:
The 8237 compatible DMA mode is selected by clearing bit DAKOLY in the
DcHardwareConfiguration register (see
shown in
Table 71:
The DMA subsystem of an IBM compatible PC is based on the Intel 8237 DMA
controller. It operates as a ‘fly-by’ DMA controller: the data is not stored in the DMA
controller, but it is transferred between an I/O port and a memory address. A typical
example of the ISP1161A1’s DC in 8237 compatible DMA mode is given in
The 8237 has two control signals for each DMA channel: DREQ (DMA Request) and
DACK (DMA Acknowledge). General control signals are HRQ (Hold Request) and
HLDA (Hold Acknowledge). The bus operation is controlled via MEMR (Memory
read), MEMW (Memory write), IOR (I/O read) and IOW (I/O write).
Endpoint
identifier
10
11
12
13
14
Symbol
DREQ2
DACK2
EOT
RD
WR
Fig 40. ISP1161A1’s device controller in 8237 compatible DMA mode.
Table
Endpoint selection for DMA transfer
8237 compatible mode: pin functions
CONTROLLER
Description
DC’s DMA request
DC’s DMA
acknowledge
end of transfer
read strobe
write strobe
ISP1161A1
DEVICE
71.
Rev. 03 — 23 December 2004
D0 to D15
EPIDX[3:0]
1011
1100
1101
1110
1111
DREQ2
DACK2
WR
RD
RAM
I/O
O
I
I
I
I
Transfer direction
EPDIR = 0
OUT: read
OUT: read
OUT: read
OUT: read
OUT: read
USB single-chip host and device controller
Table
MEMR
MEMW
DREQ
DACK
IOR
IOW
CONTROLLER
82). The pin functions for this mode are
…continued
Function
ISP1161A1’s DC requests a DMA transfer
DMA controller confirms the transfer
DMA controller terminates the transfer
instructs the ISP1161A1’s DC to put data
on the bus
instructs the ISP1161A1’s DC to get data
from the bus
DMA
8237
HLDA
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
HRQ
EPDIR = 1
IN: write
IN: write
IN: write
IN: write
IN: write
ISP1161A1
HRQ
HLDA
CPU
004aaa185
Figure
86 of 136
40.

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