ISP1161A1BM ST-Ericsson Inc, ISP1161A1BM Datasheet - Page 100

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ISP1161A1BM

Manufacturer Part Number
ISP1161A1BM
Description
IC USB HOST/DEVICE CTRLR 64-LQFP
Manufacturer
ST-Ericsson Inc
Datasheet

Specifications of ISP1161A1BM

Controller Type
USB 2.0 Controller
Interface
Parallel
Voltage - Supply
3.3V, 5V
Current - Supply
47mA
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
64-LQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
568-1163
ISP1161A1BM,557

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Philips Semiconductors
Table 88:
9397 750 13961
Product data
Bit
Symbol
Reset
Access
Bit
Symbol
Reset
Access
DcDMACounter register: bit allocation
15
7
13.1.8 Reset Device (F6H)
13.2.1 Write/Read Endpoint Buffer (R/W: 10H,12H-1FH/01H–0FH)
13.2 Data flow commands
The internal DMA counter is automatically reloaded from the DcDMACounter register
when DMA is re-enabled (DMAEN = 1). See
Code (Hex): F2/F3 — write/read DcDMACounter register
Transaction — write/read 1 word
Table 89:
This command resets the ISP1161A1 DC in the same way as an external hardware
reset via input RESET. All registers are initialized to their ‘reset’ values.
Code (Hex): F6 — reset the device
Transaction — none
Data flow commands are used to manage the data transmission between the USB
endpoints and the system microprocessor. Much of the data flow is initiated via an
interrupt to the microprocessor. The data flow commands are used to access the
endpoints and determine whether the endpoint FIFOs contain valid data.
Remark: The IN buffer of an endpoint contains input data for the host, the OUT
buffer receives output data from the host.
This command is used to access endpoint FIFO buffers for reading or writing. First,
the buffer pointer is reset to the beginning of the buffer. Following the command, a
maximum of (M + 1) words can be written or read, with M given by (N
N representing the size of the endpoint buffer. After each read/write action the buffer
pointer is automatically incremented by 2.
In DMA access, the first word (the packet length) is skipped: transfers start at the
second word of the endpoint buffer. When reading, the ISP1161A1 DC can detect the
last word via the End of Packet (EOP) condition. When writing to a bulk/interrupt
endpoint, the endpoint buffer must be completely filled before sending the data to the
host. Exception: when a DMA transfer is stopped by an external EOT condition, the
current buffer content (full or not) is sent to the host.
Bit
15 to 0
14
6
DcDMACounter register: bit description
Symbol
DMACR[15:0]
13
5
Rev. 03 — 23 December 2004
Description
DMA Counter register
12
4
DMACR[15:8]
DMACR[7:0]
R/W
R/W
00H
00H
USB single-chip host and device controller
11
3
Section 13.1.6
10
2
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
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