ISP1161A1BM ST-Ericsson Inc, ISP1161A1BM Datasheet - Page 96

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ISP1161A1BM

Manufacturer Part Number
ISP1161A1BM
Description
IC USB HOST/DEVICE CTRLR 64-LQFP
Manufacturer
ST-Ericsson Inc
Datasheet

Specifications of ISP1161A1BM

Controller Type
USB 2.0 Controller
Interface
Parallel
Voltage - Supply
3.3V, 5V
Current - Supply
47mA
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
64-LQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
568-1163
ISP1161A1BM,557

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Philips Semiconductors
Table 82:
9397 750 13961
Product data
Bit
Symbol
Reset
Access
Bit
Symbol
Reset
Access
DcHardwareConfiguration register: bit allocation
reserved
DAKOLY
R/W
R/W
15
0
7
0
DRQPOL
The DcHardwareConfiguration register controls the connection to the USB bus, clock
activity and power supply during ‘suspend’ state, output clock frequency, DMA
operating mode and pin configurations (polarity, signalling mode).
Code (Hex): BA/BB — write/read DcHardwareConfiguration register
Transaction — write/read 1 word
EXTPUL
Table 83:
Bit
15
14
13
12
11 to 8
7
6
5
4
R/W
R/W
14
0
6
1
DcHardwareConfiguration register: bit description
Symbol
-
EXTPUL
NOLAZY
CLKRUN
CLKDIV[3:0]
DAKOLY
DRQPOL
DAKPOL
EOTPOL
NOLAZY
DAKPOL
R/W
R/W
13
1
5
0
Rev. 03 — 23 December 2004
CLKRUN
EOTPOL
Description
reserved
A logic 1 indicates that an external 1.5 k pull-up resistor is
used on pin D and that SoftConnect is not used. Bus reset
value: unchanged.
A logic 1 disables output on pin CLKOUT of the LazyClock
frequency (100 kHz
causes pin CLKOUT to switch to LazyClock output after
approximately 2 ms delay, following the setting of bit GOSUSP
in the DcMode register. Bus reset value: unchanged.
A logic 1 indicates that the internal clocks are always running,
even during ‘suspend’ state. A logic 0 switches off the internal
oscillator and PLL, when they are not needed. During ‘suspend’
state this bit must be made logic 0 to meet the suspend current
requirements. The clock is stopped after a delay of
approximately 2 ms, following the setting of bit GOSUSP in the
DcMode register. Bus reset value: unchanged.
This field specifies the clock division factor N, which controls the
clock frequency on output CLKOUT. The output frequency in
MHz is given by 48 / (N + 1). The clock frequency range is
3 MHz to 48 MHz (N = 0 to 15) with a reset value of 12 MHz
(N = 3). The hardware design guarantees no glitches during
frequency change. Bus reset value: unchanged.
A logic 1 selects DACK-only DMA mode. A logic 0 selects
8237 compatible DMA mode. Bus reset value: unchanged.
Selects DREQ2 pin signal polarity (0 = active LOW, 1 = active
HIGH). Bus reset value: unchanged.
Selects DACK2 pin signal polarity (0 = active LOW).
Bus reset value: unchanged.
Selects EOT pin signal polarity (0 = active LOW, 1 = active
HIGH). Bus reset value: unchanged.
R/W
R/W
12
0
4
0
WKUPCS
USB single-chip host and device controller
R/W
R/W
11
0
3
0
50 %) during ‘suspend’ state. A logic 0
PWROFF
R/W
R/W
10
0
2
0
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
CLKDIV[3:0]
ISP1161A1
INTLVL
R/W
R/W
9
1
1
0
INTPOL
R/W
R/W
95 of 136
8
1
0
0

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