ISP1161A1BM ST-Ericsson Inc, ISP1161A1BM Datasheet - Page 32

• Manufacturer Part Number: ISP1161A1BM
• Description: IC USB HOST/DEVICE CTRLR 64-LQFP
• Manufacturer: ST-Ericsson Inc

Specifications of ISP1161A1BM

• Controller Type: USB 2.0 Controller
• Interface: Parallel
• Voltage - Supply: 3.3V, 5V
• Current - Supply: 47mA
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 64-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 568-1163; ISP1161A1BM,557

Philips Semiconductors
9397 750 13961
Product data
9.4.2 Data organization
The data transfer can be done via the PIO mode or the DMA mode. The data transfer
rate can go up to 15 Mbyte/s. In the DMA operation, the single-cycle or multi-cycle
burst modes are supported. Multi-cycle burst modes of 1, 4, or 8 cycles per burst is
supported for the ISP1161A1.
PTD data is used for every data transfer between a microprocessor and the USB bus,
and the PTD data resides in the buffer RAM. For an OUT or SETUP transfer, the
payload data is placed just after the PTD, after which the next PTD is placed. For an
IN transfer, RAM space is reserved for receiving a number of bytes that is equal to the
total bytes of the transfer. After this, the next PTD and its payload data are placed
(see
Remark:
The PTD is defined for both ATL and ITL type data transfers. For ITL, the PTD data is
put into ITL buffer RAM, and the ISP1161A1 takes care of the Ping-Pong action for
the ITL buffer RAM access.
The PTD data (PTD header and its payload data) is a structure of DWORD (double-
word or 4-byte) alignment. This means that the memory address is organized in
blocks of 4 bytes. Therefore, the first byte of every PTD and the first byte of every
payload data are located at an address which is a multiple of 4.
an example in which the first payload data is 14 bytes long, meaning that the last byte
of the payload data is at the location 15H. The next addresses (16H and 17H) are not
multiples of 4. Therefore, the first byte of the next PTD will be located at the next
multiple-of-four address, 18H.
Fig 27. Buffer RAM data organization.
Figure
27).
Rev. 03 — 23 December 2004
bottom
top
payload data of OUT transfer
payload data of OUT transfer
empty space for IN total data
PTD of OUT transfer
PTD of OUT transfer
PTD of IN transfer
USB single-chip host and device controller
RAM buffer
MGT952
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
000H
7FFH
ISP1161A1
Figure 28
illustrates
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